Configuration context switcher
View Patent ↗An IC with configuration context switchers is provided. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
1. An integrated circuit (IC) comprising:
an unclocked state element for switchably receiving different configuration data sets, wherein each received configuration data set has a logical bit comprising first and second physical bits, the first physical bit for setting the state of the unclocked state element and the second physical bit for resetting the state of the unclocked state element; and
a configurable circuit for configurably performing one of a plurality of operations based on the state of the unclocked state element.
2. The IC of claim 1 , wherein the unclocked state element is a SR latch.
3. The IC of claim 1 , wherein the unclocked state element is in an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive the different configuration data sets.
4. The IC of claim 1 further comprising a plurality of storage circuits for storing the different configuration data sets.
5. The IC of claim 4 , wherein the first and second physical bits are from a particular storage circuit that stores the first and second physical bits as a complementary pair.
6. The IC of claim 1 , wherein the unclocked state element keeps a same state when not receiving configuration data sets.
7. The IC of claim 6 , wherein the unclocked state element receives two physical bits that are pre-charged to logic high when the unclocked state element is not receiving configuration data sets.
8. A method comprising:
configuring a configurable circuit to perform an operation based on a current state of an unclocked state element, the unclocked state element having a connection to a set of storage circuits, wherein the connection comprises a reset bit and a set bit, the reset bit for resetting the unclocked state element and the set bit for setting the unclocked state element;
updating the current state of the unclocked state element when the connection is driven by the content of the set of storage circuits; and
holding the current state of the unclocked state element when the connection is not driven by the content of the set of storage circuits.
9. The method of claim 8 , wherein the unclocked state element is a SR latch.
10. The method of claim 8 , wherein the unclocked state element keeps the same current state when neither the set bit and the reset bit is asserted.
11. The method of claim 8 , wherein the unclocked state element keeps the same current state when both the set bit and the reset bit are pre-charged to logic high.
12. The method of claim 8 , wherein the unclocked state element is a toggle latch.
13. An integrated circuit (IC) comprising:
a plurality of storage circuits for storing a plurality of configuration data sets;
an interconnect circuit for retrieving different sets of configuration data from the plurality of storage circuits, wherein the retrieved configuration data set comprises a pair of physical bits for determining a current state of the interconnect circuit, wherein the interconnect circuit comprises an unclocked storage element for storing the current state of the interconnect circuit, wherein the pair of physical bits comprises a set bit for setting the unclocked storage element to logic ‘1’ and a reset bit for resetting the unclocked storage element to a logic ‘0’; and
a configurable circuit for configurably performing one of a plurality of operations based on the current state of the interconnect circuit.
14. The IC of claim 13 , wherein the pair of physical bits are both pre-charged to logic high when the interconnect circuit is not retrieving a stored set of configuration data from the plurality of storage circuits.
15. The IC of claim 13 , wherein the pair of physical bits carries two complementary binary values when the interconnect circuit is retrieving a stored set of configuration data from the plurality of storage circuits.
16. The IC of claim 13 , wherein the unclocked storage element is a SR latch.
17. The IC of claim 13 , wherein the pair of physical bits is from a particular storage circuit that stores a logical bit of a set of configuration data as a complementary physical pair.