IP Library Granted Patent US 12,366,911
Granted Patent B2
US 12,366,911 · App. 18/449,479 · Granted Jul 22, 2025

Methods and apparatus for selectively extracting and loading register states

Inventors: Shiva Rao (Belmont, CA); David Munday (Santa Cruz, CA)
Assignee: Altera Corporation
G06F1/3278G01R31/3177G06F9/30101G06F9/3012G06F9/30141G06F30/3312
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Quick Facts
Patent No.
US 12,366,911
App. No.
18/449,479
Granted
Jul 22, 2025
Kind
B2
Abstract

Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.

Claims (25)

1. A method, comprising:

running an application using registers stored in a first programmable logic device, wherein the registers comprise configuration registers that store a design of the first programmable logic device and user data registers used in the application; and

migrating a function performed by the application by conveying at least some of the configuration registers and at least some of the user data registers from the first programmable logic device to a second programmable logic device.

2. The method of claim 1 , wherein the first programmable logic device comprises a field-programmable gate array.

3. The method of claim 1 , wherein the second programmable logic device comprises a field-programmable gate array.

4. The method of claim 1 , wherein running the application comprises running the application on a first server corresponding to the registers stored in the first programmable logic device.

5. The method of claim 4 , wherein migrating the function performed by the application comprises conveying the at least some registers from the first programmable logic device of the first server to the second programmable logic device.

6. The method of claim 4 , wherein the first programmable logic device is on the first server and the second programmable logic device is on a second server.

7. The method of claim 6 , wherein migrating the function comprises moving the application from the first server to the second server.

8. The method of claim 1 , wherein migrating the function performed by the application comprises migrating at least some application code from the first programmable logic device to the second programmable logic device.

9. The method of claim 8 , wherein the application comprises a design specification for the first programmable logic device or the second programmable logic device.

10. The method of claim 1 , wherein the at least some of the user data registers are marked for inclusion in migration.

11. A system, comprising:

a first programmable logic device to store registers to support execution of an application, wherein the registers comprise configuration registers that store a design of the first programmable logic device and user data registers used in execution of the application; and

a second programmable logic device to receive at least some of the configuration registers and at least some user data registers from the first programmable logic device.

12. The system of claim 11 , wherein the first programmable logic device comprises a field-programmable gate array.

13. The system of claim 11 , wherein the second programmable logic device comprises a field-programmable gate array.

14. The system of claim 11 , comprising a first server corresponding to the first programmable logic device.

15. The system of claim 14 , comprising a second server corresponding to the second programmable logic device.

16. A method, comprising:

storing a design of a first programmable logic device in configuration registers and user registers used in an application in user data registers;

at least partially implementing the application using registers stored in the first programmable logic device, wherein the registers comprise the configuration registers and the user data registers; and

transmitting at least some of the registers from the first programmable logic device to a second programmable logic device, wherein at least some of the registers comprises at least some of the configuration registers and at least some of the user data registers.

17. The method of claim 16 , wherein transmitting the at least some of the registers comprises transferring a function performed using the application from the first programmable logic device to the second programmable logic device.

18. The method of claim 17 , wherein transmitting the at least some of the registers comprises transferring application code from a first server associated with the first programmable logic device to a second server associated with the second programmable logic device.

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2023
From: RAO, SHIVA; MUNDAY, DAVID ALEXANDER
To: ALTERA CORPORATION
Reel/Frame 065956/0983 →