Hybrid architecture for signal processing and signal processing accelerator
Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input signals from the FPGA. The array of network nodes controllably route the input signals to the array of SPAs.
1. Circuitry for use with a field programmable gate array (FPGA), the circuitry comprising:
an array of signal processing accelerators (SPAs) coupled to and separate from the FPGA, wherein the array of SPAs is configured to receive input signals from the FPGA as a hub to send data to the array of SPAs;
an array of network nodes that route the input signals to the array of SPAs;
a first connection between two SPAs of the array of SPAs that interfaces with a respective array of the array of network nodes; and
a second connection between the two SPAs that does not interface with the respective array of the array of network nodes.
2. The circuitry of 1 , wherein the array of SPAs is coupled to and separate from one or more processors that configure and update contents of the array of SPAs.
3. The circuitry of claim 2 , wherein the circuitry comprises one or more direct memory access blocks to interface between the array of nodes and the one or more processors.
4. The circuitry of claim 1 , wherein the FPGA and the array of network nodes interface using an input-output interface that writes to and from boundary wires of the FPGA.
5. The circuitry of claim 4 , wherein communication over the input-output interface utilizes a streaming protocol.
6. The circuitry of claim 5 , wherein the streaming protocol comprises an Advanced eXtensible Interface (AXI) streaming protocol.
7. The circuitry of claim 1 , wherein the input signals comprise a data word and a control word that are each transmitted over a wire between at least one of the network nodes and at least one of the SPAs.
8. The circuitry of claim 7 , wherein the data word and the control word each includes a mode bit indicative of whether the input signal corresponds to a transfer of data or a control write.
9. The circuitry of claim 7 , wherein the data word and the control word each includes a valid bit that enables writing to at least one of the SPAs.
10. The circuitry of claim 7 , wherein the control word includes a context field that determines which of a plurality of coefficient banks is to be used.
11. The circuitry of claim 10 , wherein the context field consists of two bits.
12. The circuitry of claim 1 , wherein each SPA in the array of SPAs corresponds to a network node of the array of network nodes to provide input to the respective SPA.
13. The circuitry of claim 1 , wherein each SPA in the array of SPAs corresponds to a network node of the array of network nodes to provide output from the respective SPA.
14. The circuitry of claim 1 , wherein the array of SPAs comprises a linear path through the array of SPAs where SPAs directly couple to adjacent SPAs.
15. The circuitry of claim 1 , wherein the second connection comprises a larger width connection relative to the first connection.
16. A method for manipulating data comprising
receiving input data at an array of signal processing accelerators (SPAs) from a field programmable gate array (FPGA) acting as a hub for the array of SPAs, wherein each SPA in the array of SPAs has a same architecture that is configurable to implement different functions on the input data;
routing the input data from the FPGA into the array of SPAs using an array of network nodes; and
routing data between two SPAs of the array of SPAs by selecting between a first connection between the two SPAs that interfaces with a network node and a second connection between the two SPAs that does not interface with the network node.
17. The method of claim 16 , wherein routing the input data using the array of network nodes utilizes a rectangular two-dimensional grid of the array of network nodes that includes:
a set of horizontal connections that connects horizontally adjacent network nodes that share a row in the two-dimensional grid; and
a set of vertical direct connections connect vertically adjacent network nodes that share a column in the two-dimensional grid.
18. The method of claim 16 , wherein the circuitry connects to a hard processor subsystem that provides programming instructions to the array of SPAs, and an array of direct memory access blocks that interfaces between the hard processor subsystem and the array of SPAs.
19. A data processing device comprising:
a field-programmable gate array (FPGA);
one or more processors; and
circuitry for accelerating processing of the data processing device, wherein the circuitry comprises:
an array of signal processing accelerators (SPAs) coupled to and separate from the FPGA and the one or more processors, wherein the array of SPAs is configured to receive input signals from the FPGA and the one or more processors, and the array of SPAs perform a function on the input signals rather than the FPGA or the one or more processors performing the function;
an array of network nodes that route the input signals to the array of SPAs;
a first connection between two SPAs of the array of SPAs that interfaces with a respective array of the array of network nodes; and
a second connection between the two SPAs that does not interface with the respective array of the array of network nodes.
20. The data processing device of claim 19 , wherein the second connection comprises a high bandwidth connection relative to the first connection.