Systems and methods for time-multiplexed synchronous logic

1. A processor-implemented method for multiplexing a logic circuit in time domain, the method comprising:

obtaining, via the processor, information relating to a plurality of logic circuit components, wherein the plurality of logic circuit components are built on a programmable structure; and

selectively assigning, via the processor, a first logic circuit component and a second logic circuit component from the plurality of logic circuit components, as a time-shared resource via implementation by a computer-aided design tool, wherein:

the computer-aided design tool removes unsupported clock regions from the plurality of logic circuit components;

the first logic circuit component and the second logic circuit component are related logic components that are functionally or structurally connected, dependent, or both; and

connecting, via the processor, configurable logic with the time-shared resource, wherein:

the configurable logic includes configurable receiver logic that receives an output from the time-shared resource and outputs to a plurality of output threads or configurable transmitter logic that transmits an input from a plurality of input threads to the time-shared resource.

2. The method of claim 1 , wherein the configurable transmitter or receiver logic includes soft logic built on a programmable structure.

3. The method of claim 1 , wherein the configurable transmitter or receiver logic includes a look-up table logic.

4. The method of claim 1 , wherein the first logic circuit component and the second logic circuit component are connected via an input, an output, a register, or any combination thereof.

5. The method of claim 1 , wherein the first logic circuit component and the second logic circuit component are selected from the plurality of logic circuit components based on a reduced overhead associated with the first logic circuit component and the second logic circuit component.

6. A processor-implemented method for multiplexing a logic circuit in time domain, the method comprising:

obtaining, via the processor, information relating to a plurality of logic circuit components that are functionally or structurally connected, dependent, or both, wherein the plurality of logic circuit components are built on a programmable structure;

selectively creating, via the processor, one or more time-domain multiplexed (TDM) logic models from the plurality of logic circuit components remaining once a computer-aided design tool removes unsupported clock regions from the plurality of logic circuit components;

instantiating, via the processor, the one or more time-domain multiplexed logic models to obtain performance data; and

comparing, via the processor, the performance data associated with two or more time-domain multiplexed logic models to select an optimal TDM logic model from the two or more TDM logic models.

7. The method of claim 6 , wherein the selectively creating two or more TDM logic models includes selectively adding soft transmitter or receiver logic from a programmable structure.

8. The method of claim 6 , wherein the two or more TDM logic models are created by locating common logic cones from the plurality of logic circuit components and mapping the common logic cones to a plurality of threads.

9. The method of claim 6 , wherein the performance data includes any of a maximum circuit frequency, area gain or power overhead.

10. The method of claim 6 , wherein the selectively creating two or more time-domain multiplexed (TDM) logic models further includes incrementally optimizing the two or more TDM logic models.

11. The method of claim 6 , wherein the selectively creating two or more time-domain multiplexed (TDM) logic models includes:

generating a netlist of the plurality of logic circuit components;

generating a hierarchy of the plurality of logic circuit components; and

assigning the plurality of logic circuit components to one or more threads based on the hierarchy.

12. The method of claim 6 , wherein the selectively creating two or more time-domain multiplexed (TDM) logic models includes:

configurably adding TDM registers to one or more input threads of the two or more TDM logic models.

13. The method of claim 6 , wherein the selectively creating two or more TDM logic models is performed by a computer-aided design tool.

14. Circuitry for multiplexing a logic circuit in time domain, the circuitry comprising:

time-domain multiplexed (TDM) logic generated by selectively assigning one or more related logic components as a time-shared resource via a computer-aided design tool, wherein:

the computer-aided design tool removes unsupported clock regions from the plurality of logic circuit components; and

the one or more related logic components are functionally or structurally connected, dependent, or both;

configurable transmitter soft logic transmitting an input received from one or more input threads to the TDM logic; and

configurable receiver soft logic receiving an output from the TDM logic and outputting the output to one or more output threads.

15. The circuitry of claim 14 , wherein the circuitry is built on a programmable structure.

16. The circuitry of claim 14 , wherein the one or more related logic components are connected via an input, an output, a register, or any combination thereof.

17. The circuitry of claim 14 , wherein the selectively assigning one or more related logic components as the time-shared resource is performed by a computer-aided design tool.

18. A processor-readable non-transitory medium storing processor-executable instructions for multiplexing a logic circuit in time domain, the processor-executable instructions comprising:

instructions executable by a processor to obtain information relating to a plurality of logic circuit components, wherein the plurality of logic circuit components are built on a programmable structure;

instructions executable by the processor to selectively assign, via a computer-aided design tool, a first logic circuit component and a second logic circuit component from the plurality of logic circuit components as a time-shared resource, wherein:

the computer-aided design tool removes unsupported clock regions from the plurality of logic circuit components;

the first logic circuit component and the second logic circuit component are related logic components that are functionally or structurally connected, dependent, or both; and

instructions executable by the processor to connect configurable logic with the time-shared resource, wherein:

the configurable logic includes configurable receiver logic that receives an output from the time-shared resource and outputs to a plurality of output threads or configurable transmitter logic that transmits an input from a plurality of inputs threads to the time-shared resource.