Method and apparatus for performing register retiming in the presence of timing analysis exceptions

1. A method for designing a system on a target device, comprising:

identifying a timing exception for a portion of a signal path;

identifying an area on the target device that includes components affected by the timing exception; and

performing register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area, wherein at least one of the identifying and performing is performed by a processor.

2. The method of claim 1 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path.

3. The method of claim 1 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other signal paths.

4. The method of claim 1 , wherein the timing exception comprises a multicycle that identifies how a default timing constraint may be applied differently to the portion of the signal path.

5. The method of claim 1 , wherein the timing exception comprises a false path that excuses a default timing constraint from being applied to the portion of the signal path.

6. The method of claim 1 , wherein the timing exception comprises a minimum delay and maximum delay for a signal on the portion of the signal path.

7. The method of claim 1 , wherein identifying the area that includes components affected by the timing exception comprises:

identifying a first component at a beginning of the timing exception;

identifying a second component at an end of the timing exception; and

defining the area to include the first component, the second component, and all components along the portion of the path between the first and second components.

8. The method of claim 1 further comprising:

identifying a second timing exception for a second portion of the signal path;

identifying a second area on the target device that includes components affected by the second timing exception, wherein the first position on the signal path is on one side of the second area and the second position on the signal path is on another side of the second area.

9. The method of claim 1 , wherein the register retiming reallocates delay along the signal path to allow a signal to satisfy timing requirements along the signal path.

10. The method of claim 1 , wherein the timing exception is provided by a user after timing analysis is performed on the system.

11. The method of claim 1 , wherein the timing exception is provided during design entry prior to synthesis, placement, and routing of the system.

12. The method of claim 1 , wherein register reaming is performed after synthesis, placement, and routing is performed on the system.

13. The method of claim 1 further comprising generating constraints that prevent registers residing in the area from being used for register retiming, wherein at least one of the identifying and generating is performed by a processor.

14. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system on a target device, comprising:

identifying a timing exception for a portion of a signal path;

identifying an area on the target device that includes components affected by the timing exception; and

generating constraints that prevent registers residing in the area from being used for register retiming.

15. The non-transitory computer readable medium of claim 14 further comprising performing register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area.

16. The non-transitory computer readable medium of claim 15 further comprising generating a report that identifies the register and the timing exception to a user.

17. The non-transitory computer readable medium of claim 14 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path.

18. The non-transitory computer readable medium of claim 14 , wherein the timing exception comprises a multicycle that identifies how a default timing constraint may be applied differently to the portion of the signal path.

19. The non-transitory computer readable medium of claim 14 , wherein the timing exception comprises a false path that excuses a default timing constraint from being applied to the portion of the signal path.

20. The non-transitory computer readable medium of claim 14 , wherein the timing exception comprises a minimum delay and maximum delay for a signal on the portion of the signal path.

21. A system designer, comprising:

a timing exception identification unit that identifies a timing exception for a portion of a signal path in a system;

an area identification unit that identifies an area in the system with components affected by the timing exception; and

a constraints unit that applies constraints to unallocated registers in the area to prevent the unallocated registers to be used in register retiming.

22. The system designer of claim 21 further comprising a register retiming unit to perform register retiming on the system while complying with the constraints.

23. The system designer of claim 21 , wherein the register retiming unit performs register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area.

24. The system designer of claim 21 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path.