Methods for optimizing circuit performance via configurable clock skews
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.
1. An integrated circuit comprising:
a region of circuitry supplied with clock signals by a plurality of overlapping clock networks, wherein the region of circuitry comprises a plurality of configurable logic blocks; and
a plurality of programmable delay circuits for time borrowing that provide a programmable amount of delay to clock signals to be supplied by different clock networks of the overlapping clock networks.
2. The integrated circuit of claim 1 , wherein the plurality of programmable delay circuits for time borrowing provide the programmable amount of delay to the respective clock signals before providing them to one of the overlapping clock networks.
3. The integrated circuit of claim 1 , comprising a plurality of respective clock network drivers for the plurality of overlapping clock networks, wherein the plurality of programmable delay circuits is disposed after the plurality of respective clock network drivers and before a first bifurcation of an associated tree structure.
4. The integrated circuit of claim 1 , wherein a first clock network of the plurality of overlapping clock networks is configurable to supply a first clock signal of the clock signals to the region of circuitry, wherein a second clock network of the plurality of overlapping clock networks is configurable to supply a second clock signal of the clock signals to the region of circuitry, and wherein the first clock signal has a different clock delay in relation to the second clock signal to enable time borrowing using the different clock delay.
5. The integrated circuit of claim 4 , wherein the first clock network supplies the first clock signal to a first latching circuit of the region of circuitry and wherein the second clock network supplies the second clock signal to a second latching circuit of the region of circuitry.
6. The integrated circuit of claim 5 , wherein the first latching circuit or the second latching circuit, or both, comprise a flip-flop or a pulsed latch.
7. The integrated circuit of claim 1 , wherein the region of circuitry comprises the plurality of configurable logic blocks, digital signal processing (DSP) blocks, and random access memory (RAM).
8. An article of manufacture comprising one or more tangible, non-transitory, machine-readable media that store instructions that instruct one or more processors to:
receive a circuit design for field programmable gate array (FPGA) circuitry, wherein the circuit design comprises a plurality of paths including a faster path and a slower path; and
perform a time borrowing process on the circuit design, wherein the time borrowing process comprises determining routing for clock signals supplied on overlapping clock networks that supply the clock signals to a same region of the FPGA circuitry, wherein the same region of the FPGA circuitry comprises a plurality of configurable logic blocks, to cause time to be borrowed from the faster path and given to the slower path.
9. The article of manufacture of claim 8 , wherein the time-borrowing process comprises:
determining path delays associated with the plurality of paths of the circuit design to identify at least the slower path;
determining target clock skews that, when supplied to the paths, would cause time to be borrowed from the faster path and given to the slower path; and
updating the circuit design, based at least in part on the target clock skews, to connect clock signals having different delays to configurable logic blocks of the paths, wherein the clock signals are supplied respectively via the overlapping clock networks.
10. The article of manufacture of claim 9 , wherein determining the path delays comprises determining a critical path delay.
11. The article of manufacture of claim 9 , wherein updating the circuit design comprises determining a programmable clock delay for a plurality of programmable delay circuits for time borrowing that respectively provide the programmable clock delay to the clock signals to be supplied by the different clock networks of the overlapping clock networks.
12. The article of manufacture of claim 8 , wherein the time-borrowing process is performed after placement and routing of the circuit design.
13. The article of manufacture of claim 8 , wherein the FPGA circuitry comprises the plurality of configurable logic blocks and a plurality of digital signal processing (DSP) blocks.
14. The article of manufacture of claim 8 , wherein the FPGA circuitry comprises the plurality of configurable logic blocks and one or more blocks of random access memory (RAM).
15. A method, comprising:
receiving, via at least one processor, a circuit design for field programmable gate array (FPGA) circuitry, wherein the circuit design comprises a plurality of paths including a faster path and a slower path; and
performing, via the at least one processor, a time borrowing process on the circuit design, wherein the time borrowing process comprises determining routing for clock signals supplied on at least partially overlapping clock networks that supply the clock signals to a same region of the FPGA circuitry, wherein the same region of the FPGA circuitry comprises a plurality of configurable logic blocks, to cause time to be borrowed from the faster path and given to the slower path.
16. The method of claim 15 , comprising performing the time borrowing process comprises:
determining path delays associated with the plurality of paths of the circuit design to identify at least the slower path;
determining target clock skews that, when supplied to the paths, would cause time to be borrowed from the faster path and given to the slower path; and
updating the circuit design, based at least in part on the target clock skews, to connect clock signals having different delays to configurable logic blocks of the paths, wherein the clock signals are supplied respectively via the at least partially overlapping clock networks.
17. The method of claim 16 , comprising determining the path delays comprises determining a critical path delay.
18. The method of claim 16 , comprising updating the circuit design comprises determining a programmable clock delay for a plurality of programmable delay circuits for time borrowing that respectively provide the programmable clock delay to the clock signals to be supplied by the different clock networks of the overlapping clock networks.
19. The method of claim 15 , comprising the FPGA circuitry comprises the plurality of configurable logic blocks and a plurality of digital signal processing (DSP) blocks.
20. The method of claim 15 , comprising wherein the FPGA circuitry comprises the plurality of configurable logic blocks and one or more blocks of random access memory (RAM).