Recessed vertical interconnects for device miniaturization

1. An electronic assembly comprising:

a package substrate with a first surface and an opposing second surface;

a first interconnect disposed in the package substrate and extending between the first and the second surfaces;

a second interconnect disposed in the package substrate and extending between the first and the second surfaces;

a first contact pad comprising a first recessed side coupled to a first terminal of the first interconnect; and

a subsequent first contact pad comprising a subsequent first recessed side coupled to an opposing second terminal of the first interconnect,

wherein the first interconnect comprises a first recessed side wall and the second interconnect is arranged adjacent the first recessed side wall, wherein the first and the subsequent first recessed sides are aligned with the first recessed side wall.

2. The electronic assembly of claim 1 , wherein the second interconnect is at least partially encircled by the first recessed side wall.

3. The electronic assembly of claim 1 , wherein the second interconnect further comprises a second recessed side wall extending in parallel with the first recessed side wall between the first and the second surfaces.

4. The electronic assembly of claim 3 , wherein the first and the second recessed sides face each other.

5. The electronic assembly of claim 3 , further comprising a second contact pad comprising a second recessed side coupled to a first terminal of the second interconnect, and a subsequent second contact pad comprising a subsequent second recessed side coupled to an opposing second terminal of the second interconnect, wherein the second and the subsequent second recessed sides are aligned with the second recessed side wall.

6. The electronic assembly of claim 5 , further comprising a plurality of first metal traces or planes coupled to the first and the second contact pads, and a plurality of second metal traces or planes coupled to the subsequent first and the subsequent second contact pads.

7. The electronic assembly of claim 1 , wherein the first and second interconnects are configured to facilitate a differential pair electrical signal.

8. The electronic assembly of claim 1 , wherein the first interconnect is configured to facilitate a reference voltage and the second interconnect is configured to facilitate a single-ended electrical signal.

9. A computing device comprising:

a communication chip; and

an electronic assembly coupled to the communication chip, the electronic assembly comprising:

a package substrate with a first surface and an opposing second surface;

a first interconnect disposed in the package substrate and extending between the first and the second surfaces;

a second interconnect disposed in the package substrate and extending between the first and the second surfaces;

a first contact pad comprising a first recessed side coupled to a first terminal of the first interconnect; and

a subsequent first contact pad comprising a subsequent first recessed side coupled to an opposing second terminal of the first interconnect,

wherein the first interconnect comprises a first recessed side wall and the second interconnect is arranged adjacent the first recessed side wall, wherein the first and the subsequent first recessed sides are aligned with the first recessed side wall.

10. The computing device of claim 9 , wherein the second interconnect is at least partially encircled by the first recessed side wall.

11. The computing device of claim 9 , wherein the second interconnect further comprises a second recessed side wall extending in parallel with the first recessed side wall between the first and the second surfaces.

12. The computing device of claim 11 , wherein the first and the second recessed sides face each other.

13. The computing device of claim 11 , further comprising a second contact pad comprising a second recessed side coupled to a first terminal of the second interconnect, and a subsequent second contact pad comprising a subsequent second recessed side coupled to an opposing second terminal of the second interconnect, wherein the second and the subsequent second recessed sides are aligned with the second recessed side wall.

14. A method comprising:

providing a package substrate with a first surface and an opposing second surface;

arranging a first interconnect in the package substrate, the first interconnect extending between the first and the second surfaces, wherein the first interconnect comprises a first recessed side wall;

arranging a second interconnect adjacent the first recessed side wall in the package substrate, the second interconnect extending between the first and the second surfaces;

coupling a first contact pad comprising a first recessed side to a first terminal of the first interconnect;

coupling a subsequent first contact pad comprising a subsequent first recessed side to an opposing second terminal of the first interconnect; and

aligning the first and the subsequent first recessed sides with the first recessed side wall.

15. The method of claim 14 , further comprising at least partially encircling the second interconnect by the first recessed side wall.

16. The method of claim 14 , further comprising:

forming in the second interconnect a second recessed side wall extending in parallel with the first recessed side wall between the first and the second surfaces;

coupling a second contact pad comprising a second recessed side to a first terminal of the second interconnect;

coupling a subsequent second contact pad comprising a subsequent second recessed side to an opposing second terminal of the second interconnect; and

aligning the second and the subsequent second recessed sides with the second recessed side wall.