Patent Assignment
Reel/Frame 072704/0307
Assignment of Assignor's Interest
Recorded: 2025-09-09
Pages: 23
Assignor
INTEL CORPORATION
Executed: 2025-07-21
Assignee
ALTERA CORPORATION
101 INNOVATION DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(244)
Integrated regulating scheme for HSSI architecture in programmable logic device with separate supplies
Application:
60/712,027 →
Multi-Protocol Multiple Data Rate Auto Speed Negotiation Architecture in a Programmable Device
Application:
61/305,311 →
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
Application:
17/740,057 →
Publication:
US US20230064381A1
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
Application:
18/222,989 →
Publication:
US US20230359695A1
Computer Chassis with Parallel Backplanes
Application:
15/792,431 →
Publication:
US US20190121402A1
Configurable Terminations in High-Speed Serial Links
Application:
62/551,393 →
Micro Through-Silicon via for Transistor Density Scaling
Application:
18/824,468 →
Publication:
US US20240429131A1
Micro Through-Silicon via for Transistor Density Scaling
Application:
19/248,022 →
Publication:
US US20250385161A1
Multiple Ball Grid Array (Bga) Configurations for a Single Integrated Circuit (Ic) Package
Application:
16/218,331 →
Publication:
US US20190115293A1
Multiple Ball Grid Array (Bga) Configurations for a Single Integrated Circuit (Ic) Package
Application:
17/098,000 →
Publication:
US US20210066178A1
Method to accelerate VM migration using coherent attached FPGA
Application:
62/868,242 →
Computing System for Mitigating Execution Drift
Application:
63/001,134 →
System, Method and Apparatus for Race-Condition True Random Number Generator
Application:
17/541,247 →
Publication:
US US20220100475A1
Secured Deployment of Machine Learning Models
Application:
16/913,923 →
Publication:
US US20200327454A1
Off-Package High Density, High Bandwidth Memory Access Using Optical Links
Application:
17/031,823 →
Publication:
US US20220092016A1
Embedded Faraday Rotators and Components for Increasing Bandwidth and/or Reducing Fiber Count in Photonics Multi Chip Packages
Embedded Faraday Rotators and Components for Increasing Bandwidth and/or Reducing Fiber Count in Photonics Multi Chip Packages
Application:
19/244,646 →
Publication:
US US20250317206A1
Reconfigurable Inlet Power Feed and Integrated Circuit Power
Scalable Receiver Architecture for Silicon Photonic Links
Programmable Fabric-Based Instruction Set Architecture for a Processor
Multichip Package Staircase Cavities
Application:
17/485,295 →
Publication:
US US20230101340A1
Homogenous Die Stacking With Increased Element Density
Flexible Instruction Set Architecture Supporting Varying Frequencies
Application:
19/244,789 →
Publication:
US US20250315079A1
Embedded Programmable Logic Device for Acceleration in Deep Learning-Focused Processors
Application:
17/484,439 →
Publication:
US US20220044123A1
Package Substrate with Power Delivery Network
Serdes Circuit Ctle Adaptation Using Isi Metering
Antenna Hopping for Specific Absorption Rate (Sar) Reduction
Apparatus and Method for Clock Phase Calibration
Systems And Methods For Accessing Memory Devices Using Virtual Memory Ranks
Recessed Vertical Interconnects for Device Miniaturization
Modular Low Latency Electrical Sequence for Die-to-Die Interface
Mitigation of Side Channel Attacks on Platform Interconnects Using Endpoint Hardware Based Detection, Synchronization and Re-Keying
Application:
17/954,157 →
Publication:
US US20240106644A1
System, Method and Apparatus for Peer-to-Peer Communication
Application:
17/682,015 →
Publication:
US US20220269433A1
Link Monitoring and Indication of Potential Link Failure
Method to Perform Long-Term High-Speed Link Monitoring and Maintenance
Application:
63/255,748 →
Methods and Apparatus to Perform Low Overhead Sparsity Acceleration Logic for Multi-Precision Dataflow in Deep Neural Network Accelerators
Application:
17/709,337 →
Publication:
US US20220292366A1
Segmented Row Repair for Programmable Logic Devices
Clock Gating and Clock Scaling Based on Runtime Application Task Graph Information
Application:
17/692,405 →
Publication:
US US20220197613A1
Incremental Just-in-Time (Jit) Performance Refinement for Programmable Logic Device Offload
Undercut Design with a Bonded Base Cover for Friendly Assembly and Effective Thermal Tuning of Micro-Ring Resonator (Mrr) in Open Cavity Photonic Integrated Chips (Ocpic)
Temperature Sensor to Achieve Thermal Stabilization of Micro-Ring Resonator (Mrr) in an Open Cavity Photonic Integrated Circuit (Ocpic)
On-Cavity Photonic Integrated Circuit (Ocpic) to Achieve the Most Undercut Real Estate for Effective Thermal Tuning
Systems And Methods For Securing Input/Output Data
Application:
18/089,398 →
Publication:
US US20230126961A1
Detection of Lte Enb and Ue Emitters Using Signal Processing Algorithms for Feature Recognition
Interface/Unicast for Test Content, Firmware, and Software Delivery
Data Compression in Integrated Device Network
Application:
17/957,380 →
Publication:
US US20230037575A1
Fiber Array Unit (Fau) Designs to Enable a Higher Io Bandwidth Per Unit Length and Higher Fiber Density
Application:
17/889,233 →
Publication:
US US20240061192A1
Apparatus, Device, Method, and Computer Program for Generating Logic to be Performed by Computing Circuitry of a Computing Architecture
Deep Trench Capacitor Bridge for Multi-Chip Package
Application:
17/889,395 →
Publication:
US US20240063148A1
Precoding During Link Establishment
Application:
18/143,034 →
Publication:
US US20240235906A1
Automatically Request Precoding During Link Establishment
Application:
63/433,647 →
Techniques For Increasing Activation Sparsity In Artificial Neural Networks
Undercut Architectures for Improved Thermal Efficiency in Photonic Integrated Circuit (Pic) Architectures
Application:
18/189,911 →
Publication:
US US20240319457A1
Field Replaceable Fan Assemblies for Peripheral Processing Units and Related Systems and Methods
Application:
17/957,698 →
Publication:
US US20230016098A1
Techniques For Accessing Memory Circuits
Application:
18/085,819 →
Publication:
US US20230131938A1
Photonic Integrated Circuit Edge Coupling and Fiber Attach Unit Attachment Stress Relief
Application:
18/326,458 →
Publication:
US US20240402442A1
Power and Temperature Management of Devices
Application:
17/955,183 →
Publication:
US US20230037609A1
Techniques to Share Memory Across Nodes in a System
Application:
18/127,324 →
Publication:
US US20230236995A1
Integrity-Based Implementation of Content Using Digitally Signed Secure Quick Response Code
Application:
18/058,475 →
Publication:
US US20240171403A1
Secure Boot Using Parallelization
Application:
18/147,784 →
Publication:
US US20240220626A1
System and Methods for Closed Loop Doppler Tracking in Inter-Satellite Links
Application:
17/972,965 →
Publication:
US US20240235665A9
Method and Apparatus for Enhancement of Common Mode Rejection on Coherent Optic Receivers
Application:
17/979,234 →
Publication:
US US20240146416A1
Stacked Package Design for More Reliable Fiber Coupling to Photonic Integrated Circuit
Application:
18/343,175 →
Publication:
US US20250004206A1
Virtual Platforms of Integrated Circuit Designs
Application:
18/481,935 →
Publication:
US US20240037305A1
Complex Number Matrix Multiplication Processors, Methods, Systems, and Instructions
Application:
17/985,869 →
Publication:
US US20240160443A1
Hybrid Multipy-Accumulation Operation with Compressed Weights
Application:
18/184,101 →
Publication:
US US20230229917A1
Hashing Circuit
Application:
61/922,592 →
Graph Memory Engine
Application:
19/185,014 →
Publication:
US US20250272242A1
Graph Memory Engine
Application:
62/894,454 →
TUNABLE EDGE-COUPLED INTERFACE FOR SILICON PHOTONIC INTEGRATED CIRCUITS (PICs) AND METHOD FOR MAKING SAME
Application:
18/362,033 →
Publication:
US US20250044537A1
Post-Quantum Cryptography Signature Verification
Application:
18/157,272 →
Publication:
US US20240223381A1
Post-Quantum Cryptography Signature Verification
Application:
63/477,584 →
Techniques for Infield Testing of Cryptographic Circuitry
Application:
18/106,244 →
Publication:
US US20240264231A1
Low-Power High-Performance Clock Path Architecture
Application:
18/324,872 →
Publication:
US US20240393824A1
Instructions for Floating Point Multiplication and Addition and Conversion Employing Variable Precision
Application:
18/194,327 →
Publication:
US US20240329991A1
Extended Floating-Point Range Processors, Methods, Systems, and Instructions
Application:
18/210,635 →
Publication:
US US20240419444A1
Photonics Integrated Circuit Embedded in a Glass Substrate and Optically Coupled with a Photonic Wire Bond
Application:
18/236,216 →
Publication:
US US20250067925A1
Block-Wise Pruning of Weights in Deep Neural Network
Application:
18/358,571 →
Publication:
US US20230368030A1
Device, Method and System for Communicating Between Networked Agents via a Credit Management Bus
Application:
18/375,069 →
Publication:
US US20250110813A1
Programmable Device-Based Accelerator Framework for Virtualized Environments
Application:
18/478,683 →
Publication:
US US20240031457A1
Data Clearing Attestation
Application:
18/390,958 →
Publication:
US US20240121079A1
Optical Co-Packaging on a Glass Substrate with 3D Die-Stacking
Application:
18/478,871 →
Publication:
US US20250110270A1
Optical Interconnects for Flexible Calibration of an Optical Transceiver in a Free-Space Optical Communication System
Application:
19/207,426 →
Publication:
US US20260005758A1
Technologies for an Optical Interposer with Actuator Beams
Application:
18/479,012 →
Publication:
US US20250110294A1
Current Control Systems And Methods For Communications Between Devices
Application:
18/372,696 →
Publication:
US US20250104745A1
Techniques For Arranging Conductive Pads In Electronic Devices
Application:
18/543,749 →
Publication:
US US20240120302A1
Latent Supplementary Protocol for Enhancing Performance & Functionality of Communication Systems
Application:
19/043,924 →
Publication:
US US20250184205A1
Thermal-Aware Programmable Logic Device-Based Programming
Application:
18/398,709 →
Publication:
US US20240126228A1
Lut-Free Hardware Based Softmax Accelerator
Application:
19/055,819 →
Publication:
US US20250190523A1
Two-Dimensional Actuator Beam for Adjustable Optical Coupling on Photonic Integrated Circuit Structures
Application:
18/609,860 →
Publication:
US US20250298188A1
Configurable Storage Circuits And Methods
Application:
18/746,853 →
Publication:
US US20240337692A1
Flash Adc Comparator Interpolation
Application:
18/616,729 →
Publication:
US US20250309910A1
Methods and Apparatus for Waveguide Alignment Between Optical Components
Application:
18/615,740 →
Publication:
US US20250298199A1
Block Floating Point Support
Application:
18/401,432 →
Publication:
US US20250208833A1
Block Floating Point Support
Application:
63/614,418 →
Security Techniques for Shared Use of Accelerators
Application:
18/621,950 →
Publication:
US US20240241973A1
Configurable Fpga Access Control
Application:
18/756,788 →
Publication:
US US20240345985A1
Block Number Conversion
Application:
18/401,426 →
Publication:
US US20250208865A1
Block Number Conversion
Application:
63/614,425 →
IC Device Resource Sharing
Application:
18/756,964 →
Publication:
US US20240345884A1
Block Number Dot Product
Application:
18/401,423 →
Publication:
US US20250208864A1
Block Number Dot Product
Application:
63/614,414 →
Systems and Methods for Packet Processing in Programmable Logic Devices
Application:
18/620,712 →
Publication:
US US20250310263A1
In-Field Droop Measurement and Compensation for Coherent Optical Transceiver
Application:
18/397,240 →
Publication:
US US20250219735A1
High-Throughput Low-Power Decoder
Application:
18/394,282 →
Publication:
US US20250211255A1
Coherent Reception of on/Off Keying and Pulse Position Modulations
Application:
18/397,271 →
Publication:
US US20250219740A1
Reconfigurable Deframer for Optical Communications
Application:
18/397,214 →
Publication:
US US20250219739A1
Performance Transceiver
Application:
18/754,502 →
Publication:
US US20260005721A1
Methods and Apparatus to Improve Performance of a Computing Device Implementing an Exponential Function
Application:
18/933,924 →
Publication:
US US20250060941A1
Machine Learning Control of Clock Drift
Application:
18/756,925 →
Publication:
US US20240345161A1
Data Transfer Using Coherent Doorbell Updates
Application:
18/756,818 →
Publication:
US US20240354248A1
Neural Network Accelerator Performing Operation with Mixed-Format Weights
Application:
18/931,973 →
Publication:
US US20250060940A1
Systems and Methods for Efficient Convergence for Time Servo
Application:
19/000,974 →
Publication:
US US20250132967A1
Systems and Methods for Efficient Convergence of Network-Based Clock
Application:
63/714,010 →
Multi-Level Signaling Linearity Feedback and Adjustment
Application:
19/002,449 →
Publication:
US US20250126001A1
Skewed Least Mean Square for Parameter Determination
Application:
62/943,659 →
System with Programmable Multi-Context Accelerator Circuitry
Application:
16/024,563 →
Publication:
US US20190042329A1
Programmable Device Authentication Decryption
Application:
15/940,887 →
Publication:
US US20190050603A1
Communication Protocol for Field-Programmable Gate Array (Fpga) Accelerators
Application:
62/553,460 →
Methods, Systems, and Apparatus for Detecting Respiration Phases
Application:
15/490,251 →
Publication:
US US20180296125A1
Enumerated Per Device Addressability for Memory Subsystems
Application:
62/509,353 →
Apparatus and Method for Improving Lock Time
Application:
62/530,063 →
Dynamic Memory Offlining and Voltage Scaling to Independently Bring Power Nodes Online and Offline
Application:
15/693,829 →
Publication:
US US20190073020A1
Navigation Based on Vehicle Dimensions
Application:
15/268,234 →
Publication:
US US20180080788A1
Navigation Based on Vehicle Dimensions
Application:
16/333,476 →
Publication:
US US20190265063A1
Hardware Accelerator Template and Design Framework for Implementing Recurrent Neural Networks
Application:
17/563,379 →
Publication:
US US20220121917A1
Voltage Controlled Oscillator Circuitry and Methods
Power Supply Circuitry for Data Signal Transceivers on Integrated Circuits
Patent:
7,639,993 →
Application:
11/295,391 →
Techniques for Dynamically Adjusting the Frequency Range of Phase-Locked Loops
Patent:
7,495,517 →
Application:
11/610,892 →
Pld Package with Coordinated Rfid Tag
Patent:
8,081,079 →
Application:
12/134,458 →
Pld Package with Coordinated Rfid Tag
Techniques for Power Management on Integrated Circuits
Patent:
7,638,990 →
Application:
11/754,295 →
Programmable Supply Voltage Regulator for Oscillator
Patent:
7,602,260 →
Application:
11/944,386 →
Hotsocket-Compatible Body Bias Circuitry with Power-Up Current Reduction Capabilities
Patent:
7,639,041 →
Application:
12/181,313 →
Method and Apparatus for Improving Inductor Performance Using Multiple Strands with Transposition
Patent:
7,902,953 →
Application:
12/228,956 →
Multi-Protocol Multiple-Data-Rate Auto-Speed Negotiation Architecture for a Device
Shielding Structure for Transmission Lines
Shielding Structure for Transmission Lines
Shielding Structure for Transmission Lines
Voltage-Controlled-Oscillator Circuitry with Power Supply Noise Rejection
Patent:
8,378,723 →
Application:
12/910,054 →
Electrostatic Discharge Protection Circuitry
Patent:
8,878,296 →
Application:
12/910,416 →
An Intertwined Pair of Conductive Paths Arranged in a Dielectric Stack and Having at Least Three Metal Layers
Patent:
9,131,604 →
Application:
13/078,701 →
Negative Bit Line Driver Circuitry
Patent:
9,256,266 →
Application:
13/289,953 →
Heterogeneous High-Speed Serial Interface System with Phase-Locked Loop Architecture and Clock Distribution System
Patent:
8,700,825 →
Application:
13/679,061 →
Heterogeneous High-Speed Serial Interface System with Phase-Locked Loop Architecture and Clock Distribution System
Integrated Circuit Package with Reduced Pad Capacitance
Patent:
9,245,835 →
Application:
13/955,849 →
Circuits and Methods For Variable Gain Amplifiers
Patent:
9,564,863 →
Application:
14/536,443 →
Multilayer Quality of Service (Qos) for Network Functions Virtualization Platforms
Patent:
9,378,043 →
Application:
14/724,089 →
One-Step Time Stamping Of Synchronization Packets For Networked Devices
Integrated Circuits with Complementary Non-Volatile Resistive Memory Elements
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
Integrated Circuits with in-Field Diagnostic and Repair Capabilites
Distributed and Adaptive Heterogeneous Wireless Communication Management
Detection and Disposition of Commands Methods and Apparatuses
Method and Apparatus for Host Adaptation to a Change of Persona of a Configurable Integrated Circuit Die
Variable Impedance Communication Terminal
Technologies for Efficient Reliable Compute Operations for Mission Critical Applications
Power Delivery for Embedded Interconnect Bridge Devices and Methods
Stacked Through-Silicon Vias for Multi-Device Packages
Micro Through-Silicon via for Transistor Density Scaling
Methods and Apparatus to Generate a Three-Dimensional (3D) Model for 3D Scene Reconstruction
Generating a Timestamp
Reversible Direction Thermal Cooling System
Apparatus, System and Method of Location Mapping
Diagnostic Testing of FPGAs for Safety Critical Systems
Micro Through-Silicon via for Transistor Density Scaling
Micro Through-Silicon via for Transistor Density Scaling
Micro Through-Silicon via for Transistor Density Scaling
Micro Through-Silicon via for Transistor Density Scaling
Transmitter Circuitry with N-Type Pull-Up Transistor and Low Output Voltage Swing
Enhancing Diagnostic Capabilities of Computing Systems by Combining Variable Patrolling Api and Comparison Mechanism of Variables
Management of Cache Use Requests Sent to Remote Cache Devices
Minimum Input/Output Toggling Rate for Interfaces
Low Power Advertising Mode for Sequential Image Presentation
Data and Clock Synchronization and Variation Compensation Apparatus and Method
Data and Clock Synchronization and Variation Compensation Apparatus and Method
Data and Clock Synchronization and Variation Compensation Apparatus and Method
Connectivity Between Integrated Circuit Dice in a Multi-Chip Package
Microelectronics Assembly Including Top and Bottom Packages in Stacked Configuration with Shared Cooling
High-Speed, Low Power, Low Kickback Noise Comparator Suitable for a Multi-Comparator Successive Approximation Analog-to-Digital Converter (Adc)
Hardware Accelerators and Methods for Out-of-Order Processing
Strong Arm Latch with Wide Common Mode Range
Configurable First In First Out and Deserializer Circuitry
Techniques For Determining Timestamp Inaccuracies In A Transceiver
Technologies for Providing I/O Channel Abstraction for Accelerator Device Kernels
Digital Signature Verification Engine for Reconfigurable Circuit Devices
Digital Signature Verification Engine for Reconfigurable Circuit Devices
Methods and Apparatus for Accelerating Virtual Machine Migration
Embedded Dual-Sided Interconnect Bridges for Integrated-Circuit Packages
Technologies for Providing Inter-Kernel Flow Control for Accelerator Device Kernels
Patent:
10,789,189 →
Application:
16/395,777 →
Computing System for Mitigating Execution Drift
Fast Memory for Programmable Devices
Fast Memory for Programmable Devices
System, Method and Apparatus for Race-Condition True Random Number Generator
Processor Package with Universal Optical Input/Output
Electrical and Optical Interfaces at Different Heights Along an Edge of a Package to Increase Bandwidth Along the Edge
Converting Multiple Light Signals into and Out of a Single Wavelength with Multiple Polarizations to Increase Optical Bandwidth
Chip Assemblies
Methods and Devices for Device Orientation to Improve Signal Quality and Sar Compliance
Analog Equalization with Peaking and Slope Control
Rounding Circuitry for Floating-Point Mantissas
Efficient Dual-path Floating-Point Arithmetic Operators
Apparatus and Method to Calibrate Clock Phase Mismatches
Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
Apparatus and Method for Reusing Manufacturing Content Across Multi-Chip Packages
Flexible Instruction Set Architecture Supporting Varying Frequencies
Three-Dimensional Stacked Programmable Logic Fabric and Processor Design Architecture
Per Channel Thermal Management Techniques for Stacked Memory
Systems and Methods for Device Authentication in Supply Chain
Wireless modem with software configurable multiple antenna ports
Serdes Circuit Automatic Gain Control and Convergence
Adaptive Cyclic Delay Line for Fractional-N Pll
Notch Filter Calibration in Lc Oscillators for Supply Noise Rejection
Switch Based on Load Current
Method for Data Packet Classification in a Data Communications Network
Method and Apparatus for Randomizer
Method and Apparatus for Randomizer
Graph Memory Engine
Transceiver Parameter Determination
Circuitry for Low-Precision Deep Learning
Platform Interface Layer and Protocol for Accelerators
Low Overheard High Throughput Solution for Point-to-Point Link
Technologies for Low-Power and High-Accuracy Timestamps
Apparatuses to Resolve Roles for Dual Role Serial Bus Devices
Spintronic devices, duplexers, transceivers and telecommunication devices
Signal Detection Techniques Using Clock Data Recovery
Signal Detection Techniques Using Clock Data Recovery
Implementing Device Models for Virtual Machines with Reconfigurable Hardware
Security Policy Management for a Plurality of Dies in a System-On-Chip
N-Depth Asynchronous Fifo Including a Collection of 1-Depth Fifo Cells
Confidential Verification of Fpga Code
Technologies for Memory Margin Aware Reliable Software Execution
Provision of on Premise Ambient Service Method and Apparatus
Enumerated Per Device Addressability for Memory Subsystems
Apparatus and Method for Improving Lock Time
Apparatus and Method for Improving Lock Time
Memory Read Circuit with N Type and P Type Pre-Charge
Electronic Chip with Under-Side Power Block
Generation of Distinctive Value Based on True Random Input
Monitoring Electrical Substation Networks
Method and Apparatus to Build a Monolithic Mesh Interconnect with Structurally Heterogenous Tiles
Hardware Accelerator Architecture for Processing Very-Sparse and Hyper-Sparse Matrix Data
Heterogeneous Hardware Accelerator Architecture for Processing Sparse Matrix Data with Skewed Non-Zero Distributions
Hardware Accelerator Template and Design Framework for Implementing Recurrent Neural Networks
Related Assignments
(17)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 24, 2017
From: PULIGUNDLA, SUDEEP; YOUNG, GENE F.
To: INTEL CORPORATION
Reel/Frame 043939/0716 →
Assignment of Assignor's Interest
May 7, 2018
From: RAN, ADEE OFIR
To: INTEL CORPORATION
Reel/Frame 045735/0754 →
Assignment of Assignor's Interest
Dec 13, 2018
From: HOSSAIN, MD ALTAF; NALAMALPU, ANKIREDDY; SUBBAREDDY, DHEERAJ; SOMASEKHAR, DINESH
To: INTEL CORPORATION
Reel/Frame 047764/0778 →
Assignment of Assignor's Interest
Sep 26, 2019
From: CHITLUR, NAGABHUSHAN; AGUIRRE, MARIANO; CHANG, STEPHEN S.; MENEZES, ROHAN
To: INTEL CORPORATION
Reel/Frame 050536/0811 →
Assignment of Assignor's Interest
Aug 7, 2020
From: CHUANG, CHENG-LONG; OLIYIDE, OLORUNFUNMI; WANG, RAEMIN; AHMAD, JAHANZEB
To: INTEL CORPORATION
Reel/Frame 053428/0031 →
Assignment of Assignor's Interest
Sep 20, 2020
From: JAYARAMAN, RAMKUMAR; MARIANI, RICCARDO
To: INTEL CORPORATION
Reel/Frame 053824/0079 →
Assignment of Assignor's Interest
Apr 22, 2021
From: MARIN, BRANDON C.; HOSSEINI, KAVEH; O'KEEFFE, CONOR; TANAKA, HIROKI
To: INTEL CORPORATION
Reel/Frame 056012/0190 →
Assignment of Assignor's Interest
May 26, 2021
From: KUMASHIKAR, MAHESH K.; SUBBAREDDY, DHEERAJ; THAKUR, ANSHUMAN; HOSSAIN, MD ALTAF
To: INTEL CORPORATION
Reel/Frame 056397/0450 →
Assignment of Assignor's Interest
Oct 18, 2021
From: SUBBAREDDY, DHEERAJ; THAKUR, ANSHUMAN; NALAMALPU, ANKIREDDY; HOSSAIN, MD ALTAF
To: INTEL CORPORATION
Reel/Frame 057841/0044 →
Assignment of Assignor's Interest
Oct 22, 2021
From: FOO, LOKE YIP; YEW, TEONG GUAN; CHEAH, BOK ENG
To: INTEL CORPORATION
Reel/Frame 057873/0338 →
Assignment of Assignor's Interest
Oct 27, 2021
From: JAYARAJ, NAVNEETH; MAHESHWARI, CHETAN; VILHAUER, REED; FREDRICKSON, DUSTIN
To: INTEL CORPORATION
Reel/Frame 057936/0188 →
Assignment of Assignor's Interest
Nov 12, 2021
From: HOSSEINI, KAVEH; KARHADE, OMKAR; MAHAJAN, RAVINDRANATH V.; SHUMARAYEV, SERGEY YURYEVICH
To: INTEL CORPORATION
Reel/Frame 058102/0600 →
Assignment of Assignor's Interest
Dec 20, 2021
From: LEVIN, ITAMAR; RAN, ADEE OFIR
To: INTEL CORPORATION
Reel/Frame 058963/0331 →
Assignment of Assignor's Interest
Aug 3, 2022
From: VIVEKANANDHAM, RAJESH; SUBBAREDDY, DHEERAJ; NAGARAJ, DHEEMANTH; DEGALAHAL, VIJAY S. R.
To: INTEL CORPORATION
Reel/Frame 060704/0777 →
Assignment of Assignor's Interest
Jan 8, 2024
From: ALTERA CORPORATION
To: INTEL CORPORATION
Reel/Frame 066055/0111 →
Security Interest
Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
Assignment of Assignor's Interest
Oct 21, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 072612/0159 →