IP Library Granted Patent US 11,404,094
Granted Patent B2
US 11,404,094 · App. 16/144,944 · Granted Aug 2, 2022

Transmitter circuitry with N-type pull-up transistor and low output voltage swing

Inventors: Harishankar Sridharan (Santa Clara, CA); Karthik Tyamgondlu (Chandler, AZ)
Assignee: Intel Corporation
G11C7/10G06F1/26G06F1/28G11C5/14G11C7/00G11C7/1057G11C7/1087G11C11/40G11C11/4074G11C11/4093G11C11/4096H03K17/687H03K17/6872H03K19/00H03K19/0005H03K19/0008H03K19/0013H03K19/00361H03K19/00384H03K19/0175H03K19/0185H03K19/017509H03K19/017518H03K19/017545H03K19/018521H03K19/018585H03K19/173H03K19/1733H03L7/0812
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Quick Facts
Patent No.
US 11,404,094
App. No.
16/144,944
Granted
Aug 2, 2022
Kind
B2
Abstract

An apparatus is provided, where the apparatus includes a first transistor coupled between a supply node and an output node; a resistor and a second transistor coupled in series between the output node and a ground terminal; a circuitry to receive data, and to output a first control signal and a second control signal to respectively control the first transistor and the second transistor, wherein an output signal at the output node is indicative of the data, and wherein the first transistor is a N-type transistor.

Claims (22)

1. An apparatus comprising:

a first transistor coupled between a first supply node and an output node, wherein the first transistor is an N-type transistor;

a resistive device and a second transistor coupled in series between the output node and a second supply node;

a third transistor coupled between the first supply node and the output node, wherein the third transistor is a P-type transistor;

a multiplexer to receive a first power supply and a second power supply, and output the first power supply to the first supply node in a first mode of operation and output the second power supply to the first supply node in a second mode of operation, wherein a first voltage level of the first power supply is lower than a second voltage level of the second power supply; and

a pre-driver circuitry to receive data, and to output a first control signal to control the first transistor, a second control signal to control the second transistor, and a third control signal to control the third transistor,

wherein, in the first mode of operation, the pre-driver circuitry is to turn-off the third transistor and is to use the first transistor to selectively pull-up the output node based on the data;

wherein, in the second mode of operation, the pre-driver circuitry is to turn-off the first transistor and is to use the third transistor to selectively pull-up the output node based on the data;

wherein the pre-driver circuitry includes a level shifter; and

wherein the level shifter, in the second mode of operation, changes a voltage level of the third control signal from a voltage level at which the pre-driver circuitry operates to a voltage level at which the gate of the third transistor operates.

2. The apparatus of claim 1 , wherein:

the pre-driver circuitry is to turn off the third transistor via the third control signal, in response to a voltage at the first supply node being lower than a threshold voltage.

3. The apparatus of claim 1 , wherein:

the pre-driver circuitry is to, in the first and second modes of operation, control the second transistor to selectively pull down the output node based on the data.

4. The apparatus of claim 1 , wherein:

the first voltage level is equal to, or lower than, 0.7 volts (V); and

the second voltage level is higher than 1.0 V.

5. The apparatus of claim 1 , wherein:

the apparatus is a transmitter circuitry included in one of: a memory controller that is to transmit data to a memory interface, or the memory interface that is coupled to a memory.

6. The apparatus of claim 1 , wherein:

the first and second voltage levels of the first supply node are at a higher voltage than a voltage of the second supply node; and

an output signal at the output node is indicative of the data.

Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 072704/0307 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2019
From: SRIDHARAN, HARISHANKAR; TYAMGONDLU, KARTHIK
To: INTEL CORPORATION
Reel/Frame 048241/0515 →
Cited By (1)
US 12,519,470