Micro through-silicon via for transistor density scaling
An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
1. An electronic device comprising a first integrated circuit (IC) die, the first IC die including:
a first bonding pad surface, and a first backside surface opposite the first bonding pad surface:
a first active device layer arranged between the first bonding pad surface and the first backside surface; and
at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends at least to the first active device layer, and wherein the first BSV portion has substantially vertical sidewalls.
2. The electronic device of claim 1 , including:
a package substrate, wherein the first backside surface of the first IC die is coupled to the package substrate; and
a second IC die including a second bonding pad surface and a second backside surface opposite the second bonding pad surface, wherein the second IC die is arranged on the first IC die with the second bonding pad surface facing the first bonding pad surface, and the second BSV portion of the stacked TSV is in electrical contact with the first bonding pad surface of the first IC die.
3. The electronic device of claim 2 , wherein the second IC die includes at least one stacked TSV disposed between the second backside surface and the second bonding pad surface, wherein the at least one stacked TSV of the second die includes a first BSV portion that extends to the second backside surface and a second BSV portion that has a width smaller than a width of the first BSV portion.
4. The electronic device of claim 2 , including a third IC die coupled by solder bumps to the second backside surface of the second IC die.
5. The electronic device of claim 1 , wherein the first IC die includes metal layers and via layers, and the second BSV portion extends through the metal layers and via layers.
6. The electronic device of claim 1 , wherein the first active device layer includes a plurality of transistors.
7. The electronic device of claim 1 , wherein the second BSV portion extends through the first active device layer to the first bonding pad surface.
8. The electronic device of claim 1 , wherein the first bonding pad surface of the first IC die is coupled to the second bonding pad surface of the second IC die using a plurality of solder bumps.
9. The electronic device of claim 1 , wherein the first IC die includes metal layers and via layers; and wherein the first width corresponds to a first feature pitch size of the first backside surface, and the second width corresponds to a second feature pitch size of one of the first active device layer, the metal layers, or the via layers.
10. The electronic device of claim 1 , wherein the first BSV portion and the second BSV portion each include a substantially rectangular cuboidal shape.
11. The electronic device of claim 1 , wherein the first BSV portion and the second BSV portion each a substantially cylindrical shape.