Scalable receiver architecture for silicon photonic links
Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.
1. An apparatus comprising:
sampling circuitry, coupled to photodetector circuitry, to generate a sample analog signal at a sample time based on an analog signal received from the photodetector circuitry;
equalization circuitry, coupled to the sampling circuitry, comprising a plurality of memory elements to store sample analog signals, each having a tap, to generate an equalized signal, based on the sample analog signal, comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap, wherein the third sample values are attenuated relative to the first and second sample values, and the first and second sample values correspond with two or more first symbols of a first alphabet;
data slicer circuitry, coupled to the equalization circuitry, to generate a data signal and an error signal, each based on the equalized signal; and
modulo circuitry, coupled to the data slicer circuitry, to perform a modulo operation on the two or more first symbols and to generate one or more second symbols, wherein the second symbols are according to a second alphabet.
2. The apparatus of claim 1 , wherein the first alphabet comprises a first number of symbols, the second alphabet comprises a second number of symbols, and the second number of symbols is less than the first number of symbols.
3. The apparatus of claim 1 , wherein a weighting coefficient a 0 for the cursor tap equals one, and an impulse response h FFE (n) of the equalization circuitry is approximately equal to a function of a sum of terms comprising a term δ(n), δ(n−1), and other terms, each of the other terms corresponding to a respective tap other than the cursor tap and the first postcursor tap, wherein δ represents a Dirac delta function, and wherein n is a sequence number of a signal of N sampled analog signals, wherein N is an positive integer.
4. The apparatus of claim 1 , wherein the first sample value corresponding with the cursor tap has a first amplitude, the second sample value corresponding with the first postcursor tap has a second amplitude, and the first amplitude is substantially equal to the second amplitude.
5. The apparatus of claim 1 , wherein the first sample value corresponding with the cursor tap has a first amplitude, and the sample values corresponding with taps other than the cursor tap and the first postcursor tap each have a corresponding amplitude, wherein each corresponding amplitude of the sample values corresponding with taps other than the cursor tap and the first postcursor tap is ten percent or less of the first amplitude.
6. The apparatus of claim 1 , further comprising:
clock and data recovery circuitry, coupled to the sampling circuitry, to generate sampling clock signals at sample times, wherein the sample times are offset from a center time of a symbol period to times at which a first amplitude of the first sample value corresponding with the cursor tap and a second amplitude of the second sample value corresponding with the first postcursor tap are substantially equal; and
wherein a weighting coefficient a −1 for the first postcursor tap equals zero, and an impulse response h FFE (n) of the equalization circuitry is approximately equal to a function of a sum of terms comprising a term 1*δ(n), 1*δ(n−1), and other terms, each of the other terms corresponding to a respective tap other than the cursor tap and the first postcursor tap, wherein δ represents a Dirac delta function, and wherein n is a sequence number of a signal of N sampled analog signals, wherein N is an positive integer.
7. The apparatus of claim 6 , wherein the clock and data recovery circuitry comprises:
phase detector circuitry that operates according to a phase detector function S(n) equal to a product of an error function e(n) and a difference between a signal sample x(n) and another signal sample x(n−1).
8. The apparatus of claim 6 , wherein the clock and data recovery circuitry comprises:
a phase detector of a Mueller-Muller type having a parameter to adjust phase shift, wherein the phase detector is provided with a parameter value to adjust a phase shift so that sample times are at times at which an amplitude of the first sample value is substantially equal to an amplitude of the second sample value.
9. The apparatus of claim 1 , wherein the one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap correspond with intersymbol interference (ISI).
10. The apparatus of claim 1 , wherein a receiver of the apparatus comprises the sampling circuitry, the equalization circuitry, the data slicer circuitry, the modulo circuitry, and the photodetector circuitry.
11. The apparatus of claim 1 , wherein a transmitter of the apparatus comprises a precoder, the precoder comprising a summing unit, precoder function calculation circuitry, and remainder determining circuitry, wherein:
the summing unit comprises a first input to receive a symbol value and a second input to receive an output from the precoder function calculation circuitry; and
the remainder determining circuitry comprises an input to receive an output of the summing unit and is to perform a modulo operation on the output of the summing unit, wherein an output of the remainder determining circuitry is coupled to an input of the precoder function calculation circuitry.
12. An apparatus comprising:
sampling circuitry, coupled to photodetector circuitry, to generate a first sampled signal based on an analog signal;
data slicer circuitry, coupled to the sampling circuitry, to generate a first data signal and a first error signal each based on the first sampled signal, wherein the first data signal comprises first symbols according to a first alphabet;
decoder circuitry, coupled to the data slicer circuitry, to generate a second data signal based on the first data signal and a decoder function; and
modulo circuitry, coupled to the decoder circuitry, to perform modulo operations, based on the first symbols and to generate second symbols of the second data signal, wherein the second symbols are according to a second alphabet, wherein the first alphabet comprises a first number of symbols and the second alphabet comprises a second number of symbols, and the second number is one less than the first number.
13. The apparatus of claim 12 , wherein the photodetector circuitry is coupled to an optical fiber to receive a first photonic signal via the optical fiber, and the photodetector circuitry is to generate an analog signal based on the first photonic signal.
14. The apparatus of claim 12 , wherein a receiver of the apparatus comprises the sampling circuitry, equalization circuitry, the data slicer circuitry, the modulo circuitry, and the photodetector circuitry.
15. The apparatus of claim 12 , wherein a transmitter of the apparatus comprises a precoder, the precoder comprising a summing unit, precoder function calculation circuitry, and remainder determining circuitry, wherein:
the summing unit comprises a first input to receive a symbol value and a second input to receive an output from the precoder function calculation circuitry;
the remainder determining circuitry comprises an input to receive an output of the summing unit and to perform a modulo operation on the output of the summing unit; and
the precoder function calculation circuitry comprises an input to receive an output of the remainder determining circuitry, the precoder function calculation circuitry to implement a precoder function.
16. A system comprising:
a processor and a memory to execute an operating system;
a control hub coupled to the processor;
a display device coupled to the control hub, the display device to display an image based on a display signal communicated to the display device; and
a transceiver coupled to the control hub, the transceiver comprising: sampling circuitry to generate a sample analog signal, and equalization circuitry, coupled to sampling circuitry, the equalization circuitry comprising a plurality of memory elements to store sample analog signals, each having a tap, to generate an equalized signal based on the sample analog signal, the equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and a plurality of third sample values corresponding with taps other than the cursor tap and the first postcursor tap, wherein a first amplitude of the first sample value and a second amplitude of the second sample value are substantially equal, and amplitudes of the plurality of third sample values are attenuated relative to the first and second sample values.
17. The system of claim 16 , wherein the sampling circuitry is coupled to photodetector circuitry, the sampling circuitry is to generate the sample analog signal at a sample time based on an analog signal received from the photodetector circuitry, and wherein the first and second sample values correspond with two or more first symbols of a first alphabet, the system further comprising:
data slicer circuitry, coupled to the equalization circuitry, to generate a data signal and an error signal, each based on the equalized signal; and
modulo circuitry, coupled to the data slicer circuitry, to perform a modulo operation on the two or more first symbols and to generate one or more second symbols wherein the second symbols are according to a second alphabet.
18. The system of claim 17 , wherein the first alphabet comprises a first number of symbols, the second alphabet comprises a second number of symbols, and the second number of symbols is less than the first number of symbols.
19. The system of claim 16 , wherein a weighting coefficient a 0 for the cursor tap equals one, and an impulse response h FFE (n) of the equalization circuitry is approximately equal to a function of a sum of terms comprising a term δ(n), δ(n−1), and other terms, each of the other terms corresponding to a respective tap other than the cursor tap and the first postcursor tap, wherein δ represents a Dirac delta function, and wherein n is a sequence number of a signal of N sampled analog signals, wherein N is an positive integer.
20. The system of claim 16 , further comprising:
clock and data recovery circuitry, coupled to the sampling circuitry, to generate sampling clock signals at sample times, wherein the sample times are offset from a center time of a symbol period to times at which a first amplitude of the first sample value corresponding with the cursor tap and a second amplitude of the second sample value corresponding with the first postcursor tap are substantially equal; and
wherein a weighting coefficient a−1 for the first postcursor tap equals zero, and an impulse response h FFE (n) of the equalization circuitry is approximately equal to a function of a sum of terms comprising a term 1*δ(n), 1*δ(n−1), and other terms, each of the other terms corresponding to a respective tap other than the cursor tap and the first postcursor tap, wherein δ represents a Dirac delta function, and wherein n is a sequence number of a signal of N sampled analog signals, wherein N is an positive integer.