CLOCK GATING AND CLOCK SCALING BASED ON RUNTIME APPLICATION TASK GRAPH INFORMATION

1 . An apparatus comprising:

a processor to:

receive, from a compiler, a bitstream generated from code of an application, the bitstream related to a workload of the application;

generate a task graph of the application using at least part of the bitstream, the task graph to represent one of a relationship or dependency of the code;

program the bitstream to an accelerator device, wherein the bitstream to configure the accelerator device to support the workload of the application;

execute one or more kernels of the code using the accelerator device;

identify one or more optimizations for the accelerator device based on the task graph of the application; and

transmit a command to cause the one or more optimizations to be implemented in the accelerator device.

2 . The apparatus of claim 1 , wherein the compiler comprises a data parallel programming compiler.

3 . The apparatus of claim 1 , wherein the one or more optimizations comprise at least one of clock gating or clock scaling of the accelerator device.

4 . The apparatus of claim 1 , wherein each region of the accelerator device is to execute one kernel of the one or more kernels.

5 . The apparatus of claim 1 , wherein the one or more optimizations are further based on at least one of predicted runtime metrics generated by the compiler or collected runtime metrics generated by the accelerator device when executing the one or more kernels.

6 . The apparatus of claim 5 , wherein the one or more optimizations are adaptively tuned based on the collected runtime metrics generated by the accelerator device.

7 . The apparatus of claim 1 , wherein different regions of the accelerator device receive different clock optimizations.

8 . The apparatus of claim 1 , wherein more than one optimization can be implemented at a sub-kernel level of the accelerator device.

9 . The apparatus of claim 1 , wherein the accelerator device comprises at least one a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC).

10 . The apparatus of claim 9 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

11 . A method comprising:

receiving, by a processor, a bitstream generated by a compiler from code of an application, the bitstream related to a workload of the application;

generating, by the processor, a task graph of the application using at least part of the bitstream, the task graph to represent one of a relationship or dependency of the code;

programming the bitstream to an accelerator device, wherein the bitstream to configure the accelerator device to support the workload of the application;

executing one or more kernels of the code using the accelerator device;

identifying, by the processor, one or more optimizations for the accelerator device based on the task graph of the application; and

transmitting, by the processor, a command to cause the one or more optimizations to be implemented in the accelerator device.

12 . The method of claim 11 , wherein the one or more optimizations comprise at least one of clock gating or clock scaling of the accelerator device.

13 . The method of claim 11 , wherein each region of accelerator device is to execute one kernel of the one or more kernels.

14 . The method of claim 11 , wherein the one or more optimizations are further based on at least one of predicted runtime metrics generated by the compiler or collected runtime metrics generated by the accelerator device when executing the one or more kernels.

15 . The method of claim 11 , wherein different regions of the accelerator device receive different clock optimizations.

16 . A non-transitory machine readable storage medium comprising instructions that, when executed, cause at least one processor to at least:

receive, from a compiler, a bitstream generated from code of an application, the bitstream related to a workload of the application;

generate a task graph of the application using at least part of the bitstream, the task graph to represent one of a relationship or dependency of the code;

program the bitstream to an accelerator device, wherein the bitstream to configure the accelerator device to support the workload of the application;

execute one or more kernels of the code using the accelerator device;

identify one or more optimizations for the accelerator device based on the task graph of the application; and

transmit a command to cause the one or more optimizations to be implemented in the accelerator device.

17 . The non-transitory machine readable storage medium of claim 16 , wherein the one or more optimizations comprise at least one of clock gating or clock scaling of the accelerator device.

18 . The non-transitory machine readable storage medium of claim 16 , wherein each region of the accelerator device is to execute one kernel of the one or more kernels.

19 . The non-transitory machine readable storage medium of claim 16 , wherein the one or more optimizations are further based on at least one of predicted runtime metrics generated by the compiler or collected runtime metrics generated by the accelerator device when executing the one or more kernels.

20 . The non-transitory machine readable storage medium of claim 16 , wherein different regions of the accelerator device receive different clock optimization.