STACKED PACKAGE DESIGN FOR MORE RELIABLE FIBER COUPLING TO PHOTONIC INTEGRATED CIRCUIT

1 . An integrated circuit package comprising:

a first package substrate;

a photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate;

a second package substrate coupled to a bottom side of the first package substrate; and

a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located.

2 . The integrated circuit package of claim 1 , wherein the pedestal is a first pedestal, and the integrated circuit package further comprises a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located.

3 . The integrated circuit package of claim 2 , wherein the first pedestal and second pedestal comprise different materials.

4 . The integrated circuit package of claim 1 , wherein the pedestal comprises glass or metal.

5 . The integrated circuit package of claim 1 , wherein the first package substrate comprises a cutout region and the PIC die is located at an edge defining cutout region.

6 . The integrated circuit package of claim 1 , wherein the PIC die is within a cavity in a top side of the first package substrate.

7 . The integrated circuit package of claim 1 , further comprising an electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die.

8 . The integrated circuit package of claim 1 , further comprising a processor coupled to the first package substrate and connected to the EIC die.

9 . The integrated circuit package of claim 1 , wherein the second package substrate comprises vias connected between electrical connection pads on a top side of the second package substrate and electrical connection pads on a bottom side of the second package substrate.

10 . The integrated circuit package of claim 1 , wherein the second package substrate comprises one or more of redistribution layer traces and fan-out traces.

11 . A system comprising:

an integrated circuit package comprising:

a first package substrate;

a photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate;

a second package substrate coupled to a bottom side of the first package substrate; and

a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located; and

optical fiber coupled to the PIC and on a top surface of the pedestal.

12 . The system of claim 11 , wherein the optical fiber is adhesively coupled to the pedestal.

13 . The system of claim 11 , wherein the pedestal is a first pedestal, and the system further comprises a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located, and wherein the optical fiber is further on a top surface of the second pedestal.

14 . The system of claim 11 , wherein the first package substrate comprises a cutout region and the PIC die is located at an edge defining cutout region.

15 . The system of claim 11 , wherein the PIC die is within a cavity in a top side of the first package substrate.

16 . The system of claim 11 , further comprising an electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die.

17 . The system of claim 11 , further comprising a circuit board, wherein the second package is coupled to a top side of the circuit board.

18 . A system comprising:

a circuit board;

an integrated circuit package coupled to the circuit board, the integrated circuit package comprising:

a first package substrate;

a first photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate;

a first electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die;

a second PIC die coupled to the first package substrate at the edge of the first package substrate;

a second EIC die coupled to the first package substrate and connected to the PIC die;

a processor coupled to the first EIC die and the second EIC die;

a second package substrate coupled to a top side of the circuit board and to a bottom side of the first package substrate; and

a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located;

a first fiber array unit (FAU) coupled to the first PIC and on a top surface of the pedestal; and

a second FAU coupled to the second PIC and on the top surface of the pedestal.

19 . The system of claim 18 , wherein the pedestal is a first pedestal, the system further comprises a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located, and wherein one of the first FAU or the second FAU are on a top surface of the second pedestal.

20 . The system of claim 19 , further comprising a third pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located, wherein the first FAU is on the top surface of the second pedestal and the second FAU is on a top surface of the third pedestal.