N-depth asynchronous FIFO including a collection of 1-depth FIFO cells
Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first-in first-out (FIFO) cells included in an asynchronous FIFO unit and first and second circuits included in the asynchronous FIFO unit. The first circuit provides first information based on a value of a first bit from each of the FIFO cells in order to select one of the FIFO cells to be a selected FIFO cell for storing data information in the selected FIFO cell. The second circuit provides information based on a value of a second bit from each of the FIFO cells in order to select one of the FIFO cells to be a selected FIFO cell for reading data information from the selected FIFO cell.
1. An apparatus comprising:
a first first-in first-out (FIFO) cell included in a FIFO unit to provide a first signal and a second signal; the first FIFO cell to change a value of the first signal when data information is stored in the first FIFO cell, to change a value of the second signal when data information is read from the first FIFO cell, and to provide a third signal based on the values of the first and second signals to indicate whether the first FIFO cell is available to store data information;
a second FIFO cell included in the FIFO unit to provide a fourth signal and a fifth signal, the second FIFO to change a value of the fourth signal when data information is stored in the second FIFO, to change a value of the fifth signal when data information is read from the second FIFO cell, and to provide a sixth signal based on the values of the fourth and fifth signals to indicate whether the second FIFO cell is available to store data information; and
a circuit included in the FIFO unit to provide a seventh signal based on the third and sixth signals to indicate whether the FIFO unit is available to store data information.
2. The apparatus of claim 1 , wherein:
the first FIFO cell is to provide an eighth signal based on the values of the first and second signals to indicate whether the first FIFO cell is available to be read;
the second FIFO cell is to provide a ninth signal based on the values of the fourth and fifth signals to indicate whether the second FIFO cell is available to be read; and
an additional circuit included in the FIFO unit to provide a tenth signal based on the eighth and ninth signals to indicate whether the FIFO unit is available to be read.
3. The apparatus of claim 2 , wherein:
the first circuit is to provide an eleventh signal based on the values of the first and fourth signals to indicate whether the first FIFO cell is selected to store information; and
the second circuit is to provide a twelfth signal based on the values of the second and fifth signals to indicate whether the first FIFO cell is selected to be read.
4. The apparatus of claim 1 , wherein:
the first FIFO cell includes a register to store a value if new data information is stored in the first FIFO cell while the third signal has a value indicating that the first FIFO cell is unavailable to store data information; the value stored in the register and the value of the third signal being a same value; and
the second FIFO cell includes a register to store a value if new data information is stored in the second FIFO cell while the sixth signal has a value indicating that the second FIFO cell is unavailable to store data information, the value stored in the register of the second FIFO cell and the value of the sixth signal being a same value.
5. The apparatus of claim 2 , wherein:
the first FIFO cell includes a register to store a value if data information is read from the first FIFO cell while the eighth signal has a value indicating that the first FIFO cell is unavailable to be read, the value stored in the register and the value of the eighth signal being a same value; and
the second FIFO cell includes a register to store a value if data information is read from the second FIFO cell while the ninth signal has a value indicating that the second FIFO cell is unavailable to be read, the value stored in the register of the second FIFO and the value of the eighth signal being a same value.
6. The apparatus of claim 1 , wherein:
the first FIFO unit is available to store information when the first and second signals have a same value, and the first FIFO unit is unavailable to store information when the first and second signals have different values; and
the second FIFO unit is available to store information when the fourth and fifth signals have a same value, and the second FIFO unit is unavailable to store information when the fourth and fifth signals have different values.
7. The apparatus of claim 2 , wherein:
the first FIFO unit is available to be read when the first and second signals have different values, and the first FIFO unit is unavailable to be read when the first and second signals have a same value; and
the second FIFO unit is available to be read when the fourth and fifth signals have different value, and the second FIFO unit is unavailable to be read when the fourth and fifth signals have a same value.
8. The apparatus of claim 1 , wherein the first FIFO cell is to:
change the value of the first signal from a first value to a second value when information is stored in the first FIFO cell in a first write operation; and
change the value of the first signal from the second value to the first value when information is stored in the first FIFO cell in a second write operation.
9. The apparatus of claim 8 , wherein the first value is binary one and the second value is binary zero.
10. The apparatus of claim 1 , wherein the first FIFO cell is to:
change the value of the second signal from a first value to a second value when information is read from the first FIFO cell in a first read operation; and
change the value of the second signal from the second value to the first value when information is read from the first FIFO cell in a second read operation.
11. The apparatus of claim 10 , wherein the first value is binary one and the second value is binary zero.
12. An apparatus comprising:
first-in first-out (FIFO) cells included in FIFO unit, each of the FIFO cells to provide a first signal, a second signal, and a third signal;
a selected FIFO cell of the FIFO cells to change a value of the first signal provided by the selected FIFO cell when information is stored in a memory location, to change a value of the second signal provided by the selected FIFO cell when information is read from the memory location, and to change a value of each of the third and a fourth signal provided by the selected FIFO cell when one of the first and second signals of the selected FIFO cell changes;
a first circuit included in the FIFO unit to provide a first status signal based on the value of the third signal from each of the FIFO cells to indicate whether the FIFO unit is available to store information; and
a second circuit included in the FIFO unit to provide a second status signal based on the value of the fourth signal from each of the FIFO cells to indicate whether the FIFO unit is available to be read.
13. The apparatus of claim 12 , wherein the selected FIFO cell is to change the value of the each of the first and second signals between a first value and a second value; the first value corresponds to binary zero, and the second value corresponds to a binary one.
14. The apparatus of claim 12 , wherein the memory location is included in a dual-port random access memory (RAM) circuit.
15. An apparatus comprising:
conductive lines on a circuit board;
an antenna coupled to the conductive lines;
a device coupled to the conductive lines; the device including an asynchronous first-in first-out (FIFO) unit, the FIFO unit including:
a first first-in first-out (FIFO) cell included in a FIFO unit to provide a first signal and a second signal, the first FIFO cell to change a value of the first signal when data information is stored in the first FIFO cell, to change a value of the second signal when data information is read from the first FIFO cell, and to provide a third signal based on the values of the first and second signals to indicate whether the first FIFO cell is available to store data information;
a second FIFO cell included in the FIFO unit to provide a fourth signal and a fifth signal, the second FIFO to change a value of the fourth signal when data information is stored in the second FIFO, to change a value of the fifth signal when data information is read from the second FIFO cell, and to provide a sixth signal based on the values of the fourth and fifth signals to indicate whether the second FIFO cell is available to store data information; and
a circuit included in the FIFO unit to provide a seventh signal based on the third and sixth signals to indicate whether the FIFO unit is available to store data information.
16. The apparatus of claim 15 , wherein the device includes a processor.
17. The apparatus of claim 15 , further comprising a connector coupled to at least one of the conductive lines and the device, the conductor conforming with at least one of Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Ethernet, and Peripheral Component Interconnect Express (PCIe) specifications.