High-speed, low power, low kickback noise comparator suitable for a multi-comparator successive approximation analog-to-digital converter (ADC)
A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.
1. An analog-to-digital-converter (ADC) apparatus for data center applications, comprising:
a successive approximation register (SAR) analog-to-digital-converter (ADC) to provide a digital value that represents an analog input voltage, and to make successive comparisons to improve accuracy of the digital value, the SAR ADC comprising a comparator, the comparator comprising an input differential pair and circuitry to keep the input differential pair's respective source and drain nodes at a same voltage when the comparator is entering and exiting a comparison state thereby reducing kickback noise.
2. The ADC apparatus of claim 1 wherein the comparator comprises a tail circuit to pull current through a latch circuit in parallel with a current sink or source of the input differential pair.
3. The ADC apparatus of claim 1 wherein an upper supply voltage rail of the comparator is set to a voltage that is less than a supply voltage rail of another analog circuit on a same semiconductor die as the comparator.
4. The ADC apparatus of claim 1 wherein the SAR ADC is positioned at a front receiving end of a network interface.
5. The ADC apparatus of claim 4 wherein the network interface is an Ethernet interface.
6. The ADC apparatus of claim 1 wherein the SAR ADC is integrated within any of:
a network switch system;
a network router system.
7. The ADC apparatus of claim 1 wherein a current sink or source of the input differential pair is to receive a fixed bias so that large voltage changes on respective source nodes of the input differential pair is avoided.
8. The ADC apparatus of claim 1 wherein the comparator comprises a tail circuit coupled to a latch circuit to pull current through the latch circuit in parallel with a current sink or source of the input differential pair.
9. A comparator, comprising:
an input differential pair and circuitry to keep the input differential pair's respective source and drain nodes at a same voltage when the comparator is entering and exiting a comparison state thereby reducing kickback noise.
10. The comparator of claim 9 wherein the comparator comprises a tail circuit to pull current through a latch circuit in parallel with a current sink or source of the input differential pair.
11. The comparator of claim 10 wherein an upper supply voltage rail of the comparator is set to a voltage that is less than a supply voltage rail of another analog circuit on a same semiconductor die as the comparator.
12. The comparator of claim 9 wherein the comparator is integrated into a SAR ADC, wherein, the SAR ADC is positioned at a front receiving end of a network interface.
13. The comparator of claim 12 wherein the network interface is an Ethernet interface.
14. The comparator of claim 9 wherein the comparator is integrated within any of:
a network switch system;
a network router system.
15. The comparator of claim 9 wherein a current sink or source of the input differential pair is to receive a fixed bias so that large voltage changes on respective source nodes of the input differential pair is avoided.
16. The comparator of claim 9 wherein the comparator comprises a tail circuit coupled to a latch circuit to pull current through the latch circuit in parallel with the current sink or source of the input differential pair.
17. A computing system, comprising:
a plurality of processing cores;
a system memory;
a system memory controller between the plurality of processing cores and the system memory;
a network interface comprising an ADC SAR, the ADC SAR comprising a comparator, the comparator comprising an input differential pair and circuitry to keep the input differential pair's respective source and drain nodes at a same voltage when the comparator is entering and exiting a comparison state thereby reducing kickback noise.
18. The computing system of claim 17 wherein the comparator comprises a tail circuit to pull current through a latch circuit in parallel with a current sink or source of the input differential pair.
19. The computing system of claim 18 wherein an upper supply voltage rail of the comparator is set to a voltage that is less than a supply voltage rail of another analog circuit on a same semiconductor die as the comparator.
20. The computing system of claim 17 wherein a current sink or source of the input differential pair is to receive a fixed bias so that large voltage changes on respective source nodes of the input differential pair is avoided.