Digital signature verification engine for reconfigurable circuit devices

1. An apparatus comprising:

one or more processors; and

a reconfigurable circuit device, the reconfigurable circuit device including:

a plurality of digital signal processing (DSP) blocks, each DSP block including an integer multiplier circuit,

a plurality of logic elements (LEs), and

an embedded memory;

wherein the one or more processors are to configure the reconfigurable circuit device to operate as a digital signature verification engine for a bit stream, the digital signature verification engine including:

a hybrid multiplication unit, the hybrid multiplication unit combining a set of the plurality of LEs and a set of the plurality of DSP blocks to multiply operands for signature verification, wherein the hybrid multiplication unit is to iterate a portion of a calculation a plurality of times to generate a product of a multiplication operation for a digital signature verification operation, including storing intermediate results of the calculation in the embedded memory.

2. The apparatus of claim 1 , wherein the reconfigurable circuit device is one of an FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device).

3. The apparatus of claim 1 , wherein the digital signature verification engine is an ECDSA (Elliptic Curve Digital Signature Algorithm) engine.

4. The apparatus of claim 3 , wherein the hybrid multiplication unit is to perform multiplication for Galois field computations.

5. The apparatus of claim 3 , wherein the embedded memory of the reconfigurable circuit device includes a block random access memory (BRAM), and wherein configuring the reconfigurable circuit device to operate as a signature verification engine for a bit stream includes the one or more processors to configure two memory blocks in the BRAM for duplicate data entries.

6. The apparatus of claim 3 , wherein the digital signature verification engine is to receive a hash of a bitstream for verification.

7. The apparatus of claim 3 , wherein configuring the reconfigurable circuit device to operate as a digital signature verification engine for a bit stream includes the one or more processors to provide curve parameters, a public key, and a signature for the digital signature verification engine.

8. The apparatus of claim 1 , wherein the hybrid multiplication unit performs a 384-bit×384-bit multiplication operation.

9. The apparatus of claim 8 , wherein each DSP block includes a 9-bit×9-bit multiplier, and wherein the hybrid multiplication unit utilizes 43 DSP blocks to provide a 384-bit×9-bit multiplier to iteratively calculate the 384-bit×384-bit multiplication operation.

10. One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

configuring a reconfigurable circuit device to operate as a digital signature verification engine for a bit stream, the reconfigurable circuit device including a plurality of digital signal processing (DSP) blocks, each DSP block including an integer multiplier circuit, a plurality of logic elements (LEs), and an embedded memory;

generating a hash of a bit stream; and

performing a signature verification for the bit stream utilizing the digital signature verification engine;

wherein the digital signature verification engine includes a hybrid multiplication unit, the hybrid multiplication unit combining a set of the plurality of LEs and a set of the plurality of DSP blocks to multiply operands for the signature verification, and wherein the hybrid multiplication unit is to iterate a portion of a calculation a plurality of times to generate a product of a multiplication operation for a digital signature verification operation, including storing intermediate results of the calculation in the embedded memory.

11. The one or more mediums of claim 10 , wherein the reconfigurable circuit device is one of an FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device).

12. The one or more mediums of claim 10 , wherein configuring the reconfigurable circuit device to operate as a digital signature verification engine for a bit stream includes configuring the reconfigurable circuit device to operate as an ECDSA (Elliptic Curve Digital Signature Algorithm) engine.

13. The one or more mediums of claim 12 , wherein the hybrid multiplication unit is to perform multiplication for Galois field computations.

14. The one or more mediums of claim 12 , wherein the embedded memory of the reconfigurable circuit device further includes a block random access memory (BRAM), and wherein configuring the reconfigurable circuit device to operate as a signature verification engine for a bit stream includes configuring two memory blocks in the BRAM for duplicate data entries.

15. The one or more mediums of claim 12 , wherein configuring the reconfigurable circuit device to operate as a digital signature verification engine for a bit stream includes providing curve parameters, a public key, and a signature for the digital signature verification engine.

16. A computing system comprising:

one or more processors;

dynamic random access memory (DRAM) for storage of data; and

an FPGA (Field Programmable Gate Array), the FPGA including:

a block random access memory (BRAM),

a plurality of digital signal processing (DSP) blocks, each DSP block including an integer multiplier circuit, and

a plurality of logic elements (LEs);

wherein the one or more processors are to configure the FPGA as an ECDSA (Elliptic Curve Digital Signature Algorithm) engine for signature verification of a bit stream, the ECDSA engine including:

a hybrid multiplication unit, the hybrid multiplication unit combining a set of the plurality of LEs and a set of the plurality of DSP blocks to multiply operands for the signature verification, wherein the hybrid multiplication unit is to iterate a portion of a calculation a plurality of times to generate a product of a multiplication operation for an ECDSA operation, including storing intermediate results of the calculation in the BRAM.

17. The computing system of claim 16 , wherein the hybrid multiplication unit is to perform multiplication for Galois field computations.

18. The computing system of claim 16 , configuring the FPGA as an ECDSA engine includes the one or more processors to configure two memory blocks in the BRAM for duplicate data entries.

19. The computing system of claim 16 , wherein configuring the FPGA as an ECDSA engine includes the one or more processors to curve parameters, a public key, and a signature for the ECDSA engine.