Granted Patent B2

US 12,309,007 · App. 17/127,853 · Granted May 20, 2025

Inventors: Itamar Levin (Holon, IL); Tali Warshavsky Grafi (Ramat Gan, IL); Marco Cusmai (Tel Aviv, IL); Ajay Balankutty (Hillsboro, OR); Shiva Kiran (Beaverton, OR); Ariel Cohen (Modiin-Maccabim-Reut, IL)

Assignee: Intel Corporation

H04L25/03878

Abstract

Claims (31)

1. An apparatus comprising:

at least one medium to communicate a signal; and

an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises in a single equalization stage:

a resonant circuit comprising an inductor, a resistance, and a capacitance;

a first source-degeneration network comprising a first tunable capacitance in parallel with a first tunable resistance; and

a second source-degeneration network comprising a second tunable capacitance in parallel with a second tunable resistance.

2. The apparatus of claim 1 , wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope.

3. The apparatus of claim 2 , wherein the independently tunable parameters of the analog equalization circuit further include a low frequency de-emphasis amount.

4. The apparatus of claim 1 , wherein the resistance is to tune a peak frequency gain.

5. The apparatus of claim 4 , wherein the resistance comprises two equal resistance segments coupled between differential outputs of the analog equalization circuit, wherein the two resistance segments are respectively coupled to a common mode voltage.

6. The apparatus of claim 4 , wherein the second tunable resistance is to tune a low frequency deemphasis amount of the analog equalization circuit.

7. The apparatus of claim 1 , wherein the first tunable capacitance is to tune a mid-range frequency response slope.

8. The apparatus of claim 1 , wherein the inductor is a first inductor and the analog equalization circuit comprises:

the first inductor, the first inductor coupled between a first output and a first portion of the resistance; and

a second inductor coupled between a second output and a second portion of the resistance.

9. The apparatus of claim 1 , wherein the inductor is coupled between a first tunable resistor and a second tunable resistor, wherein the inductor, first tunable resistor, and second tunable resistor are coupled between a first output and a second output of the analog equalization circuit.

10. A system comprising:

a receiver front end comprising:

at least one medium to communicate a signal; and

an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises:

a tunable resistor in series with an inductor, the tunable resistor to tune a peak frequency gain; and

a tunable capacitor to tune a mid-range frequency response slope.

11. The system of claim 10 , further comprising an analog to digital converter (ADC) to convert an output of the analog equalization circuit to a digital signal.

12. The system of claim 11 , further comprising a digital equalization circuit to perform equalization on an output of the ADC.

13. The system of claim 10 , further comprising an analog decision-feedback equalizer.

14. The system of claim 10 , further comprising a processor unit comprising a central processing unit, graphics processing unit, accelerator, field programmable gate array, neural network processing unit, artificial intelligence processing unit, inference engine, data processing unit, or infrastructure processing unit.

15. The system of claim 14 , further comprising at least one of a battery, display, or network interface controller communicatively coupled to the processor unit.

16. A method comprising:

adjusting tunable parameters of an analog equalization circuit to perform equalization on a signal, wherein the tunable parameters include a low frequency de-emphasis amount and a mid-range frequency response slope, wherein an adjustment of the low frequency de-emphasis amount does not change the mid-range frequency response slope, wherein the tunable parameters further include a peak frequency gain and the method comprises setting a first tunable resistance to tune the peak frequency gain.

17. The method of claim 16 , further comprising setting a second tunable resistance to tune the low frequency de-emphasis amount.

18. The method of claim 16 , further comprising setting a tunable capacitance to tune the mid-range frequency response slope.

Assignments (4)

Continuity (1)

References Cited (21)