Micro through-silicon via for transistor density scaling
An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
1. An integrated circuit (IC) package, comprising:
a package substrate;
a base IC die coupled to the package substrate, the base IC die comprising:
a silicon substrate having an active device layer and a backside surface opposite the active device layer;
a plurality of metal layers above the active device layer, the plurality of metal layers comprising an uppermost metal layer, a second to uppermost metal layer below the uppermost layer, a third to uppermost metal layer below the second to uppermost metal layer, and a fourth to uppermost metal layer below the third to uppermost metal layer;
a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and through the fourth to uppermost metal layer, the TSV having a top surface below the third to uppermost metal layer, and the TSV having a first width where the TSV extends through the active device layer, and a second width in the silicon substrate, the second width greater than the first width; and
a via between and in contact with the top surface of the TSV and an interconnect of the third to uppermost metal layer; and
a microbump coupled to an interconnect of the uppermost metal layer.
2. The IC package of claim 1 , wherein the second width in the silicon substrate is proximate to the backside surface of the silicon substrate.
3. The IC package of claim 1 , wherein the second width in the silicon substrate is at a midpoint of the silicon substrate, the midpoint between the active device layer and the backside surface.
4. The IC package of claim 1 , further comprising:
a top die coupled to the base die.
5. The IC package of claim 1 , wherein the TSV has a third width at a location in the silicon substrate, the third width less than the second width.
6. The IC package of claim 1 , further comprising:
a keep-out-region along sides of the TSV.
7. The IC package of claim 1 , wherein the TSV comprises copper.
8. An integrated circuit (IC) package, comprising:
a package substrate;
a base IC die coupled to the package substrate, the base IC die comprising:
a silicon substrate having an active device layer and a backside surface opposite the active device layer;
a plurality of metal layers above the active device layer, the plurality of metal layers comprising a topmost metal layer and a bottommost metal layer;
a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and to a location between the uppermost metal layer and the bottommost metal layer, the TSV having a first width where the TSV extends through the active device layer, and a second width in the silicon substrate, the second width greater than the first width; and
a via between and in contact with a top surface of the TSV and a metal layer between the uppermost metal layer and the bottommost metal layer; and
a microbump coupled to an interconnect of the uppermost metal layer.
9. The IC package of claim 8 , wherein the second width in the silicon substrate is proximate to the backside surface of the silicon substrate.
10. The IC package of claim 8 , wherein the second width in the silicon substrate is at a midpoint of the silicon substrate, the midpoint between the active device layer and the backside surface.
11. The IC package of claim 8 , further comprising:
a top die coupled to the base die.
12. The IC package of claim 8 , wherein the TSV has a third width at a location in the silicon substrate, the third width less than the second width.
13. The IC package of claim 8 , further comprising:
a keep-out-region along sides of the TSV.
14. The IC package of claim 8 , wherein the TSV comprises copper.
15. A system, comprising:
a package substrate;
a base IC die coupled to the package substrate, the base IC die comprising:
a silicon substrate having an active device layer and a backside surface opposite the active device layer;
a plurality of metal layers above the active device layer, the plurality of metal layers comprising an uppermost metal layer, a second to uppermost metal layer below the uppermost layer, a third to uppermost metal layer below the second to uppermost metal layer, and a fourth to uppermost metal layer below the third to uppermost metal layer;
a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and through the fourth to uppermost metal layer, the TSV having a top surface below the third to uppermost metal layer, and the TSV having a first width where the TSV extends through the active device layer, and a second width in the silicon substrate, the second width greater than the first width; and
a via between and in contact with the top surface of the TSV and an interconnect of the third to uppermost metal layer;
a microbump coupled to an interconnect of the uppermost metal layer;
a top die coupled to the base die;
a plurality of solder balls coupled to a side of the package substrate opposite the base IC die; and
a plurality of passive electronic components coupled to the side of the package substrate opposite the base IC die.
16. The system of claim 15 , wherein the second width in the silicon substrate is proximate to the backside surface of the silicon substrate.
17. The system of claim 15 , wherein the second width in the silicon substrate is at a midpoint of the silicon substrate, the midpoint between the active device layer and the backside surface.
18. The system of claim 15 , wherein the TSV has a third width at a location in the silicon substrate, the third width less than the second width.
19. The system of claim 15 , further comprising:
a keep-out-region along sides of the TSV.
20. The system of claim 15 , wherein the TSV comprises copper.