IP Library Granted Patent US 10,223,149
Granted Patent B2
US 10,223,149 · App. 15/380,793 · Granted Mar 5, 2019

Implementing device models for virtual machines with reconfigurable hardware

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,223,149
App. No.
15/380,793
Granted
Mar 5, 2019
Kind
B2
Abstract

A processor includes an interface coupled to a programmable integrated circuit (IC) and a processor core coupled to the interface and to execute a virtual machine monitor (VMM). The VMM provides a virtual device for a virtual machine (VM). The virtual device emulates a hardware interface of a hardware device, wherein the processor core is further to execute the VM to transmit a command through the interface to the programmable IC to update a device model, stored in the programmable IC, for the virtual device.

Claims (51)

1. A processor comprising:

a first hardware interface coupled to a programmable integrated circuit (IC);

a processor core coupled to the first hardware interface and to execute a virtual machine monitor (VMM), the VMM to provide a virtual device for a virtual machine (VM), wherein the virtual device emulates a second hardware interface of a hardware device that is coupled to the processor core, wherein the processor core is further to execute the VM to transmit a command through the first hardware interface to the programmable IC to update a device model, stored in the programmable IC, for the virtual device; and

wherein the processor core is further to execute the VMM to

detect the command associated with a VMM device model, the VMM device model corresponding to the device model stored in the programmable IC;

retrieve, from the programmable IC, a plurality of parameters stored for the device model; and

perform, using the plurality of parameters, a translated operation directed to the second hardware interface.

2. The processor of claim 1 , wherein the programmable IC is a field-programmable gate array (FPGA).

3. The processor of claim 1 , wherein the command comprises a request for access to a port of the second hardware interface, and wherein the VMM is further to:

receive the request from the programmable IC, the request including a plurality of parameters of the device model needed to fulfill the request; and

perform, using the plurality of parameters, the translated operation directed to the port of the second hardware interface.

4. The processor of claim 3 , wherein the translated operation is a virtual input/output (TO) operation to set up a physical TO operation through the port of the second hardware interface.

5. The processor of claim 3 , wherein the second hardware interface comprises a host bus adapter.

6. The processor of claim 1 , wherein the virtual device is a virtual disk, wherein the hardware device is a hard disk drive, wherein the command is directed to a port of the second hardware interface and comprises a write command to a numbered sector of the virtual disk, and wherein the write command comprises a plurality of parameters comprising one or more of: a number of sectors, a logical sector address, a physical memory address of data to be written, or a period of time for timeout before failure.

7. A system comprising:

a programmable integrated circuit (IC) to store and execute a device model; and

a processor coupled to the programmable IC, the processor to:

execute a virtual machine monitor (VMM), the VMM to provide a virtual device for a virtual machine (VM), wherein the virtual device emulates a hardware interface of a hardware device; and

execute the VM to transmit a command to the programmable IC to update the device model for the virtual device;

wherein the processor is further to execute the VMM to:

detect the command associated with a VMM device model, the VMM device model corresponding to the device model stored in the programmable IC;

retrieve, from the programmable IC, a plurality of parameters stored for the device model; and

perform, using the plurality of parameters, a translated operation directed to the hardware interface.

8. The system of claim 7 , wherein the programmable IC is a programmable Application-Specific Integrated Circuit (ASIC).

9. The system of claim 7 , wherein the command comprises a request to access the virtual device for access to the hardware interface, and wherein the programmable IC is to:

detect the command;

determine that data in a plurality of fields of the device model are available to complete the request; and

transmit the request, which includes the data, to the VMM to perform the translated operation.

10. The system of claim 9 , wherein the VMM is further to perform, using the data, the translated operation directed to the hardware interface.

11. The system of claim 9 , wherein the translated operation is a virtual input/output (TO) operation to set up a physical TO operation through a port of the hardware interface.

12. The system of claim 9 , wherein the hardware interface comprises a host bus adapter.

13. The system of claim 7 , wherein the programmable IC is to:

retrieve the plurality of parameters from the command; and

update a field of the device model with a corresponding parameter of the plurality of parameters.

14. The system of claim 7 , wherein the virtual device is a virtual disk, the hardware device is a hard disk drive, the command is directed to a port of the hardware interface and comprises a write command to a numbered sector of the virtual disk, and wherein the write command comprises the plurality of parameters comprising one or more of: a number of sectors, a logical sector address, a physical memory address of data to be written, or a period of time for timeout before failure.

15. A method comprising:

executing, by a processor core coupled to a first hardware interface, a virtual machine monitor (VMM), the VMM to provide a virtual device for a virtual machine (VM), wherein the virtual device emulates a second hardware interface of a hardware device;

detecting, by the processor core, a programmable integrated circuit (IC) coupled to the interface;

executing, by the processor core, the VM to transmit a command through the first hardware interface to the programmable IC to update a device model, stored in the programmable IC, for the virtual device;

detecting, by the VMM, the command associated with a VMM device model, the VMM device model corresponding to the device model stored in the programmable IC;

retrieving, by the VMM, from the programmable IC, a plurality of parameters stored for the device model; and

performing, by the VMM using the plurality of parameters, a translated operation directed to the second hardware interface.

16. The method of claim 15 , further comprising:

retrieving, by the programmable IC, the plurality of parameters from the command; and

updating, by the programmable IC, a field of the device model with a corresponding parameter of the plurality of parameters.

17. The method of claim 15 , wherein the command comprises a request to access the virtual device requiring access to the second hardware interface, the method further comprising:

detecting the command;

determining, by the programmable IC, that data in a plurality of fields of the device model are available to complete the request;

transmitting, by the programmable IC, the request to the VMM, the request including the data; and

performing, by the processor core executing the VMM and using the data, the translated operation directed to the second hardware interface.

18. The method of claim 17 , wherein the translated operation is a virtual input/output (TO) operation to set up a physical IO operation through a port of the second hardware interface.

Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 072704/0307 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2016
From: SCHOENBERG, SEBASTIAN
To: INTEL CORPORATION
Reel/Frame 040668/0781 →