UNDERCUT ARCHITECTURES FOR IMPROVED THERMAL EFFICIENCY IN PHOTONIC INTEGRATED CIRCUIT (PIC) ARCHITECTURES
In one embodiment, a photonic integrated circuit (PIC) device includes conductive pads on a surface of the PIC and a micro ring resonator (MRR) with a heater element centrally located between the conductive pads. The PIC also includes a cavity defined within a substrate of the PIC below the MRR, and a plurality of holes defined between the MRR and the conductive pads. The holes extend from a top surface of the PIC into the cavity, and each hole is between a respective conductive pad and the MRR.
1 . An apparatus comprising:
a substrate;
one or more dielectric layers on the substrate;
a first conductive pad on the dielectric layers;
a second conductive pad on the dielectric layers;
an optical circuit element in one of the dielectric layers, the optical circuit element between the first conductive pad and the second conductive pad;
a cavity defined within the substrate below the optical circuit element;
a first hole defined through the dielectric layers and into the cavity, the first hole formed between the first conductive pad and the optical circuit element; and
a second hole defined through the dielectric layers and into the cavity, the second hole formed between the second conductive pad and the optical circuit element.
2 . The apparatus of claim 1 , wherein the optical element is centrally located between the first hole and the second hole.
3 . The apparatus of claim 1 , wherein a center of the first hole is aligned with a center of the first conductive pad and a center of the optical circuit element, and a center of the second hole is aligned with a center of the second conductive pad and a center of the optical circuit element.
4 . The apparatus of claim 1 , further comprising:
a third conductive pad on the dielectric layers;
a fourth conductive pad on the dielectric layers;
a third hole defined through the dielectric layers and into the cavity, the third hole formed between the third conductive pad and the optical circuit element; and
a fourth hole defined through the dielectric layers and into the cavity, the fourth hole formed between the fourth conductive pad and the optical circuit element.
5 . The apparatus of claim 4 , further comprising:
a fifth hole defined through the dielectric layers and into the cavity, the fifth hole formed between the first hole and the third hole;
a sixth hole defined through the dielectric layers and into the cavity, the sixth hole formed between the second hole and the fourth hole;
a seventh hole defined through the dielectric layers and into the cavity, the seventh hole formed between the first hole and the fourth hole; and
an eighth hole defined through the dielectric layers and into the cavity, the eighth hole formed between the second hole and the third hole.
6 . The apparatus of claim 5 , wherein a center of the fifth hole is aligned with a center of the optical circuit element and a center of the sixth hole, a center of the seventh hole is aligned with a center of the optical circuit element and a center of the eighth hole.
7 . The apparatus of claim 4 , wherein the optical element is centrally located between the first hole, the second hole, the third hole, and the fourth hole.
8 . The apparatus of claim 1 , wherein the cavity is not defined under the conductive pads.
9 . The apparatus of claim 1 , wherein the optical circuit element is a micro ring resonator (MRR) with a heater element.
10 . A photonic integrated circuit (PIC) device, comprising:
conductive pads on a surface of the PIC;
a micro ring resonator (MRR) with a heater element, wherein the MRR is centrally located between the conductive pads;
a cavity defined within a substrate of the PIC below the MRR; and
a plurality of holes defined between the MRR and the conductive pads, the plurality of holes extending from a top surface of the PIC into the cavity, each hole between a respective conductive pad and the MRR.
11 . The PIC device of claim 10 , wherein the MRR is centrally located between the plurality of holes.
12 . The PIC device of claim 10 , wherein a center of each hole of the plurality of holes is aligned with a center of its respective conductive pad and the optical circuit element.
13 . The PIC device of claim 10 , wherein the plurality of holes is a first set of holes and the PIC further comprises a second set of holes extending from the top surface of the PIC device into the cavity, each hole of the second set of holes formed between a pair of holes of the first set of holes.
14 . The PIC device of claim 10 , wherein the cavity is not defined under the conductive pads.
15 . The PIC device of claim 10 , further comprising conductive traces connecting the conductive pads to the optical circuit element.
16 . The PIC device of claim 10 , further comprising optical waveguides connected to the MRR, each optical waveguide between two of the plurality of holes.
17 . An integrated circuit package comprising:
a package substrate;
an electronic integrated circuit (EIC); and
a photonic integrated circuit (PIC) coupled to the EIC, wherein the PIC comprises:
conductive pads on a surface of the PIC;
a micro ring resonator (MRR) with a heater element, wherein the MRR is centrally located between the conductive pads;
a cavity defined within a substrate of the PIC below the MRR; and
a plurality of holes defined between the MRR and the conductive pads, the plurality of holes extending from a top surface of the PIC into the cavity, each hole between a respective conductive pad and the MRR.
18 . The integrated circuit package of claim 17 , wherein the EIC and PIC are coupled via bridge circuitry in the package substrate.
19 . The integrated circuit package of claim 17 , wherein the EIC and PIC are directly coupled.
20 . The integrated circuit package of claim 17 , wherein the PIC is embedded within a cavity of the package substrate.