Systems and Methods for Efficient Convergence for Time Servo
Systems and methods for packet-based network clock synchronization are provided. An integrated circuit device may include a local clock and a packet-based synchronization servo to apply a control loop to synchronize the local clock with a remote clock. The control loop may include a frequency correction to accelerate convergence.
1 . An integrated circuit device comprising:
a local clock; and
a packet-based synchronization servo configured to apply a control loop to synchronize the local clock with a remote clock, wherein the control loop comprises a frequency correction to accelerate convergence.
2 . The integrated circuit device of claim 1 , wherein the servo is configured to determine the frequency correction based on timestamped packets received over a plurality of windows.
3 . The integrated circuit device of claim 2 , wherein the servo is configured to determine the frequency correction based on a least-squares fit to information provided by the timestamped packets received over the plurality of windows.
4 . The integrated circuit device of claim 2 , wherein the servo is configured to determine the frequency correction based on a weighted combination of pseudo-delay of a Sync direction corresponding to packets received from a master device comprising the remote clock and pseudo-delay of a Delay direction corresponding to packets sent to the master device from the integrated circuit device.
5 . The integrated circuit device of claim 4 , wherein the servo is configured to determine the pseudo-delay of the Sync direction and the pseudo-delay of the Delay direction separately.
6 . The integrated circuit device of claim 4 , wherein the servo is configured to determine the weight for each direction separately.
7 . The integrated circuit device of claim 4 , wherein the servo is configured to determine the weight for each direction as inversely proportional to a noise power estimate of that direction.
8 . The integrated circuit device of claim 2 , wherein the plurality of windows comprises windows of different sizes, wherein an initial window of the plurality of windows is smaller than a subsequent window of the plurality of windows.
9 . The integrated circuit device of claim 1 , wherein the frequency correction is received from a source external to the integrated circuit device.
10 . The integrated circuit device of claim 9 , wherein the frequency correction is based on Synchronous Ethernet (SyncE).
11 . The integrated circuit device of claim 1 , wherein the servo is configured to determine the frequency correction based on packets selected according to one of a plurality of selection methods with a lowest variance.
12 . A method comprising:
performing packet exchange of time-synchronization packets over a window size for a set of iterations;
using the time-synchronization packets in a control loop of a time-synchronization servo to control a local clock;
when synchronization convergence is not achieved over the window size for the set of iterations, increasing the window size and repeating the method until synchronization convergence is achieved or until a maximum window size or maximum set of iterations is reached.
13 . The method of claim 12 , comprising increasing the set of iterations when the window size is increased.
14 . The method of claim 12 , wherein the method is performed according to IEEE 1588 Precision Time Protocol.
15 . The method of claim 12 , comprising aligning a frequency of the local clock to a frequency of a network clock on which the time-synchronization packets are based.
16 . The method of claim 12 , comprising loading a frequency offset into an integral control word of the time-synchronization servo at start-up.
17 . The method of claim 12 , wherein using the time-synchronization packets comprises using a least-squares fit over the window size to determine a frequency offset estimate to determine a frequency correction of the local clock in relation to a network clock on which the time-synchronization packets are based.
18 . A method comprising:
receiving a plurality of time-synchronization packets over a network in accordance with a time-synchronization protocol;
determining a variance of a plurality of packet-selection methods using the plurality of time-synchronization packets; and
using a packet-selection method with a lowest variance from among the plurality of packet-selection methods to perform network time-synchronization.
19 . The method of claim 18 , wherein the plurality of packet-selection methods comprises a minimum, an average, a floor, a straight-line fit, or percentile coverage, or any combination thereof.
20 . The method of claim 18 , wherein performing network time-synchronization comprises determining and applying a frequency correction to a control loop.