Systems And Methods For Securing Input/Output Data
Methods and systems are provided for decrypting and/or encryption information received by and/or transmitted from an integrated circuit (IC) device input/output (I/O) interface. A decryption circuit is configurable to apply a first decryption algorithm selected from a plurality of decryption algorithms to received information. An encryption circuit is configurable to apply a first encryption algorithm selected from a plurality of encryption algorithms to transmitted information. A key wrapping circuit is configurable to wrap decryption and/or encryption keys associated with the first decryption and/or encryption algorithm. A firewall circuit is configurable to prevent unauthorized access to the wrapped decryption and/or encryption keys. The decryption and/or encryption circuits are reconfigurable to apply a second decryption algorithm and/or a second encryption algorithm to the received information and/or the transmitted information.
1 . An integrated circuit (IC) device comprising:
an interface to receive a first bitstream from outside of the IC device and to transmit a second bitstream outside of the IC device;
a decryption circuit configurable to apply a first decryption algorithm selected from a plurality of decryption algorithms to the first bitstream to decrypt the first bitstream; and
an encryption circuit configurable to apply a first encryption algorithm selected from a plurality of encryption algorithms to the second bitstream to encrypt the second bitstream.
2 . The IC device of claim 1 , further comprising a selection circuit configurable to:
configure the decryption circuit to apply the first decryption algorithm to decrypt the first bitstream; or
configure the encryption circuit to apply the first encryption algorithm to encrypt the second bitstream.
3 . The IC device of claim 1 , further comprising a key wrapping circuit configured to:
receive a decryption key associated with the first decryption algorithm or an encryption key associated with the first encryption algorithm; and
apply a key wrapping encryption algorithm to the decryption key or the encryption key to encrypt the decryption key or the encryption key using a wrapping encryption key to generate a wrapped decryption key and/or a wrapped encryption key.
4 . The IC device of claim 3 , further comprising an entropy source circuit configurable to generate the wrapping encryption key.
5 . The IC device of claim 3 , further comprising a firewall circuit configurable to prevent unauthorized access to the wrapped decryption key or the wrapped encryption key.
6 . The IC device of claim 1 , wherein the IC device comprises a programmable logic device (PLD), field-programmable gate array (FPGA) device, application specific integrated circuit (ASIC) device, random access memory (RAM) device, or graphics processing unit (GPU) device.
7 . The IC device of claim 2 , wherein the selection circuit is further configurable to:
reconfigure the decryption circuit to apply a second decryption algorithm that is different than the first decryption algorithm to decrypt the first bitstream; or
reconfigure the encryption circuit to apply a second encryption algorithm that is different than the first encryption algorithm to encrypt the second bitstream.
8 . A method for using an integrated circuit device, comprising:
receiving a first bitstream from outside the integrated circuit device;
applying a first decryption algorithm to the first bitstream to decrypt the first bitstream using a decryption circuit that is configurable to select the first decryption algorithm from a plurality of decryption algorithms;
transmitting a second bitstream outside of the IC device; and
applying a first encryption algorithm to the second bitstream to encrypt the second bitstream using an encryption circuit that is configurable to select the first encryption algorithm from a plurality of encryption algorithms.
9 . The method of claim 8 , further comprising configuring a selection circuit of the integrated circuit device to:
configure the decryption circuit to apply the first decryption algorithm to decrypt the first bitstream; or
configure the encryption circuit to apply the first encryption algorithm to encrypt the second bitstream.
10 . The method of claim 8 , further comprising:
receiving a decryption key associated with the first decryption algorithm or an encryption key associated with the first encryption algorithm; and
applying a key wrapping encryption algorithm to the decryption key or the encryption key to encrypt the decryption key or the encryption key using a wrapping encryption key and generate a wrapped decryption key or a wrapped encryption key.
11 . The method of claim 10 , further comprising generating the wrapping encryption key using an entropy source circuit.
12 . The method of claim 10 , further comprising preventing unauthorized access to the wrapped decryption key or the wrapped encryption key using a firewall circuit.
13 . The method of claim 8 , wherein the integrated circuit device comprises a programmable logic device (PLD), field-programmable gate array (FPGA) device, application specific integrated circuit (ASIC) device, random access memory (RAM) device, or graphics processing unit (GPU) device.
14 . The method of claim 9 , further comprising configuring the selection circuit to:
reconfigure the decryption circuit to apply a second decryption algorithm that is different from the first decryption algorithm to decrypt the first bitstream; or
reconfigure the encryption circuit to apply a second encryption algorithm that is different from the first encryption algorithm to encrypt the second bitstream.
15 . A non-transitory computer-readable storage medium comprising instructions stored thereon for causing an integrated circuit device to execute a method for configuring the integrated circuit device, the method comprising:
configuring a decryption circuit of the integrated circuit device to apply a first decryption algorithm selected from a plurality of decryption algorithms to a first bitstream to decrypt the first bitstream; and
configuring an encryption circuit of the integrated circuit device to apply a first encryption algorithm selected from a plurality of encryption algorithms to a second bitstream to encrypt the second bitstream.
16 . The non-transitory computer-readable storage medium of claim 15 , wherein the method further comprises configuring a selection circuit of the integrated circuit device to:
configure the decryption circuit to apply the first decryption algorithm to decrypt the first bitstream; or
configure the encryption circuit to apply the first encryption algorithm to encrypt the second bitstream.
17 . The non-transitory computer-readable storage medium of claim 15 , wherein the method further comprises configuring a key wrapping circuit of the integrated circuit device to:
receive a decryption key associated with the first decryption algorithm or an encryption key associated with the first encryption algorithm; and
apply a key wrapping encryption algorithm to the decryption key or the encryption key to encrypt the decryption key or the encryption key using a wrapping encryption key and generate a wrapped decryption key or a wrapped encryption key.
18 . The non-transitory computer-readable storage medium of claim 17 , wherein the method further comprises configuring an entropy source circuit of the integrated circuit device to generate the wrapping encryption key.
19 . The non-transitory computer-readable storage medium of claim 17 , wherein the method further comprises configuring a firewall circuit of the integrated circuit device to prevent unauthorized access to the wrapped decryption key or the wrapped encryption key.
20 . The non-transitory computer-readable storage medium of claim 15 , wherein the integrated circuit device comprises a programmable logic device (PLD), field-programmable gate array (FPGA) device, application specific integrated circuit (ASIC) device, random access memory (RAM) device, or graphics processing unit (GPU) device.
21 . The non-transitory computer-readable storage medium of claim 16 , wherein the method further comprises configuring the selection circuit to:
reconfigure the decryption circuit to apply a second decryption algorithm that is different than the first decryption algorithm to decrypt the first bitstream; or
reconfigure the encryption circuit to apply a second encryption algorithm that is different than the first encryption algorithm to encrypt the second bitstream.