Programmable fabric-based instruction set architecture for a processor
A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Specifically, a buffer of the extension architecture may be used to load data to and store data from the programmable fabric.
1 . An integrated circuit device comprising:
a processor comprising:
a register to store information that is processed in the processor;
a decode unit to decode instructions for the processor;
extension architecture coupled to the decode unit that is configured to receive the instructions from the decode unit, wherein the extension architecture comprises:
a first computation grid comprising a grid of fused-multiply-add circuits tuned to a first format of data;
a second computation grid comprising a programmable fabric that receives data in a second format of data different than the first format and pre-loads multiple configurations for multiple extension architectures upon boot of the processor; and
control circuitry to receive the decoded instructions as a command, select the first computation grid or the second computation grid, and selectively transmit the command to the first computation grid or the second computation grid, wherein the selection of the first computation grid or the second computation grid is based on the command; and
an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
receiving a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
validating the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor; and
storing the configuration bitstream to the programmable fabric.
2 . The integrated circuit device of claim 1 , wherein the extension architecture comprises an advanced matrix extension (AMX) architecture to integrate the second computation grid into the processor.
3 . The integrated circuit device of claim 2 , wherein the register comprises a two-dimensional register associated with the AMX architecture.
4 . The integrated circuit device of claim 1 , wherein the second format of data comprises INT8.
5 . The integrated circuit device of claim 1 , wherein the first computation grid comprises an accelerator that the processor uses to offload some processing from a core of the processor.
6 . The integrated circuit device of claim 1 , wherein the programmable fabric of the second computation grid converts the data to the first format or a third format from the second format.
7 . The integrated circuit device of claim 1 , wherein the second computation grid comprises an accelerator that the processor uses to offload some processing from a core of the processor.
8 . The integrated circuit device of claim 1 , wherein the second computation grid is disposed monolithically on a piece of semiconductor that also has other portions of the processor disposed thereon.
9 . The integrated circuit device of claim 1 , wherein the second computation grid comprises a die that is separate from one or more dies hosting other portions of the processor.
10 . A semiconductor device, comprising:
a first computation grid comprising a programmable fabric; and
a processor comprising:
a plurality of cores; and
extension architecture that is configured to receive a command from a core of the plurality of cores, wherein the extension architecture comprises:
a data buffer;
a second computation grid comprising a grid of fused-multiply-add circuits tuned to a first format of data, wherein the programmable fabric receives data in a second format of data different than the first format and pre-loads multiple configurations for multiple extension architectures upon boot of the processor; and
control circuitry to receive the command, select the first computation grid or the second computation grid, and selectively transmit the command to the first computation grid or the second computation grid, wherein the selection of the first computation grid or the second computation grid is based on a type of the command; and
a decode unit to decode instructions for the processor;
an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
receiving a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
validating the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor; and
storing the configuration bitstream to the programmable fabric.
11 . The semiconductor device of claim 10 , wherein the processor comprises a data cache unit that loads tile data in the data buffer that is to be processed in the first computation grid or the second computation grid and stores data from the data buffer that has been processed in the first computation grid or the second computation grid.
12 . The semiconductor device of claim 10 , wherein the first computation grid:
pulls data from the data buffer;
processes the data; and
stores the processed data to the data buffer.
13 . The semiconductor device of claim 12 , wherein pulling data from the data buffer comprises translating from a first clock domain of the processor to a second clock domain of the programmable fabric.
14 . The semiconductor device of claim 10 , wherein the second computation grid:
pulls data from the data buffer;
processes the data; and
stores the processed data to the data buffer.
15 . The semiconductor device of claim 10 , wherein the data buffer comprises a two-dimensional buffer for storing matrices in two-dimensional registers of the data buffer.
16 . The semiconductor device of claim 10 , wherein the extension architecture comprises architecture for an advanced matrix extension (AMX) architecture of the processor that integrates the first computation grid into the processor.
17 . The semiconductor device of claim 10 , wherein the first computation grid is logically embedded in the extension architecture as logically part of the processor.
18 . The semiconductor device of claim 17 , wherein the extension architecture and the first computation grid are implemented on different semiconductor dies.
19 . The semiconductor device of claim 17 , wherein the extension architecture and the first computation grid are implemented monolithically on a same semiconductor chip.
20 . A method comprising:
loading multiple configurations for multiple extension architectures upon boot of a processor into a programmable fabric;
receiving, at control circuitry of extension architecture of the processor, a command from a core of the processor;
based on a command type of the command, identifying a first computation grid or a second computation grid as a target of the command;
based on identification of the first computation grid as the target of the command, transmitting the command to the programmable fabric of the first computation grid, wherein the command pertains to data in a first format that is different than a second format to which a second computation grid of the processor is tuned;
receiving results for the command from the programmable fabric after conversion to the second format;
transmitting the results to the core;
receiving, at an execution unit of the processor, a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
validating, by the processor, the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor; and
storing, by the processor, the configuration bitstream to the programmable fabric.
21 . The method of claim 20 comprising:
receiving a second command from the core, wherein the second command corresponds to a second command type; and
based at least in part on the second command type, transmitting the second command to the second computation grid.
22 . The method of claim 21 , wherein the second command type comprises multiply or add using the second format.
23 . The method of claim 22 , wherein the first format comprises INT8.
24 . The method of claim 22 , wherein the command type comprises a translation from the first format to the second format.
25 . The method of claim 20 , wherein receiving the command comprises receiving data corresponding to the command at a data buffer of the extension architecture.
26 . The method of claim 25 , wherein the data buffer is a two-dimensional data buffer of an advanced matrix extension (AMX) of the processor that integrates the programmable fabric into the processor.
27 . The method of claim 25 , wherein transmitting the command comprises the programmable fabric retrieving the data from the data buffer.
28 . The method of claim 27 comprising operating on the data in the programmable fabric based on a loaded configuration of the programmable fabric.
29 . The method of claim 28 comprising loading in the loaded configuration after a reset of the processor.
30 . The method of claim 27 , wherein receiving the results from the programmable fabric comprises the programmable fabric saving the results to the data buffer.
31 . The method of claim 30 , wherein transmitting the results to the core comprises the core loading the results from the data buffer via a data cache of the processor.
32 . A semiconductor device comprising:
a programmable fabric; and
a processor comprising:
extension architecture that embeds the programmable fabric in the processor and comprises a register used to exchange data between the programmable fabric and the processor, wherein the extension architecture comprises a grid of fused-multiply-add circuits tuned to a first format of data, wherein the programmable fabric receives data in a second format of data different than the first format, and the programmable fabric pre-loads multiple configurations for multiple extension architectures upon boot of the processor;
a decode unit to decode instructions for the processor and the programmable fabric; and
an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
performing a first task using the programmable fabric when the data is received in the second format;
generating or receiving an indication to switch to a second task for the processor;
determining whether the second task utilizes the programmable fabric;
when the second task does not utilize the programmable fabric, switching to the second task without saving a state of the programmable fabric in response to the indication before switching;
receiving a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
validating the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor; and
storing the configuration bitstream to the programmable fabric.
33 . The semiconductor device of claim 32 comprising memory, wherein the operations comprise, when the second task utilizes the programmable fabric:
saving the state of the programmable fabric to memory; and
switching to the second task after saving the state of the programmable fabric to memory.
34 . The semiconductor device of claim 32 , wherein the operations comprise periodic saves of the state of the programmable fabric independent of the indication.
35 . The semiconductor device of claim 32 , wherein the extension architecture comprises an advanced matrix extension (AMX) of the processor.
36 . The semiconductor device of claim 32 , wherein the programmable fabric converts the data from the second format to the first format for use in the fused-multiply-add circuits of the processor.
37 . The method of claim 20 , wherein transmitting the results to the core comprises:
converting the data to the second format from the first format in the programmable fabric;
transmitting the data in the second format to the second computation grid; and
performing mathematical operations on the data in the second computation grid to generate the results.