Flexible instruction set architecture supporting varying frequencies

1. A processor comprising:

a CPU comprising one or more processor cores operating based on a CPU clock frequency;

a PLD communicatively coupled to the CPU operating based on a first PLL clock frequency provided by a first PLL, wherein the first PLL is configurable to provide a first PLL clock frequency up to a maximum PLL clock frequency of the first PLL; and

a first fractional PLL communicatively coupled to the CPU and the PLD wherein the first fractional PLL performs clock synchronization operations comprising:

receive an indication of the CPU clock frequency;

receive an indication of the maximum PLL clock frequency;

determine the first PLL clock frequency below the maximum PLL clock frequency, wherein the CPU clock frequency is an integer multiple value of the first PLL clock frequency;

provide an indication of the first PLL clock frequency to the first PLL to set the first PLL clock frequency; and

provide a clock ratio between the CPU clock frequency and the first PLL clock frequency to the CPU to enable the CPU to communicate with the PLD, wherein the clock ratio is based on the integer multiple value.

2. The processor of claim 1 , wherein the CPU and the PLD communicate data using the first PLL clock frequency.

3. The processor of claim 2 , wherein the CPU transmits and receives data using a number of clock cycles of the CPU clock frequency based on the clock ratio.

4. The processor of claim 1 , wherein the CPU clock frequency is higher than the maximum PLL clock frequency.

5. The processor of claim 1 , wherein the PLD comprises one or more computation grids.

6. The processor of claim 1 , wherein the PLD comprises a state machine to:

provide an indication of the maximum PLL clock frequency to the first fractional PLL; and

receive an indication of the first PLL clock frequency from the first fractional PLL.

7. The processor of claim 1 , wherein the PLL may comprise the first fractional PLL implemented thereto.

8. The processor of claim 1 , wherein the first fractional PLL is positioned between the CPU and the PLL.

9. The processor of claim 1 , wherein the first fractional PLL is implemented using programmable circuitry, hardened circuitry, processing circuitry, any combination thereof, or any other viable circuitry, to perform the clock synchronization operations.

10. The processor of claim 1 , comprising:

a plurality of PLLs comprising the first PLL, each of the plurality of PLLs providing a respective PLL clock frequency to a portion of the PLD; and

a plurality of fractional PLLs including the first fractional PLL, each of the plurality of fractional PLLs is associated with a respective PLL of the plurality of PLLs to perform clock synchronization operations.

11. A method comprising:

receiving, by a fractional PLL of a processor, an indication of a CPU clock frequency of a CPU of the processor;

receiving, by the fractional PLL, an indication of maximum clock frequency of a PLD of the processor;

determining, by the fractional PLL, a PLL clock frequency for the PLD below the maximum clock frequency of the PLD, wherein the CPU clock frequency is an integer multiple value of the PLL clock frequency;

providing, by the fractional PLL, an indication of the PLL clock frequency to the PLD to set a clock frequency of the PLL of the PLD; and

providing, by the fractional PLL, a clock ratio to the CPU to enable the CPU to communicate with the PLD, wherein the clock ratio is based on the integer multiple value.

12. The method of claim 11 , wherein the CPU clock frequency is higher than the maximum clock frequency of the PLD.

13. The method of claim 11 , wherein the maximum clock frequency of the PLD corresponds to a maximum clock frequency of the PLL of the PLD.

14. The method of claim 11 , wherein the clock ratio indicates a ratio between the CPU clock frequency and the PLL clock frequency and the CPU communicates with the PLD using the PLL clock frequency based on receiving the clock ratio.

15. The method of claim 11 , wherein the PLD performs operations using the PLL clock frequency.

16. The method of claim 11 , wherein the fractional PLL is implemented on the PLD, wherein the fractional PLL facilitates asynchronous communication between the CPU and the PLD.

17. The method of claim 11 , wherein the fractional PLL is implemented using dedicated circuitry on the processor, wherein the fractional PLL facilitates synchronous communication between the CPU and the PLD.

18. An integrated circuit device comprising:

one or more processing cores, a PLD, and a fractional PLL communicatively coupled using an Instruction Set Architecture (ISA), wherein the fractional PLL sets a PLL clock frequency of the PLD based on a core clock frequency of the one or more processing cores and provides a clock ratio between the core clock frequency and the PLL clock frequency to at least one processing core of the one or more processing cores to enable the at least one processing core to communicate with the PLD.

19. The integrated circuit device of claim 18 , wherein the core clock frequency is a multiple integer value of the PLL clock frequency.

20. The integrated circuit device of claim 19 , wherein the fractional PLL provides the clock ratio indicative of the multiple integer value to enable communication between the one or more processing cores and the PLD within the ISA of the integrated circuit.

21. The integrated circuit device of claim 18 , wherein the one or more processing cores communicate data with the PLD using the set PLL clock frequency based on receiving the clock ratio.

22. The integrated circuit device of claim 18 , wherein the fractional PLL receives an indication of the core clock frequency and an indication of a maximum clock frequency of the PLD and sets the PLL clock frequency to a fraction of the core clock frequency that is below the maximum clock frequency of the PLD.