INSTRUCTIONS FOR FLOATING POINT MULTIPLICATION AND ADDITION AND CONVERSION EMPLOYING VARIABLE PRECISION

1 . An apparatus comprising:

decoder circuitry to decode an instruction, the instruction to indicate at least one source floating-point vector, a destination storage location, and at least one value, the source floating-point vector to have a plurality of floating-point data elements, the at least one value to indicate at least one of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; or (d) any combination thereof; and

execution circuitry coupled with the decoder circuitry, the execution circuitry to perform operations according to the instruction, including to:

interpret the floating-point data elements consistent with the at least one value;

perform an operation specified by the instruction on the at least one source floating-point vector to generate a result floating-point vector; and

store the result floating-point vector in the destination storage location.

2 . The apparatus of claim 1 , wherein the at least one value is to indicate at least the exponent bias information.

3 . The apparatus of claim 2 , wherein the exponent bias information is either an exponent bias or an exponent bias offset.

4 . The apparatus of claim 2 , wherein one of:

the floating-point data elements are 16-bit floating-point data elements, having five exponent bits, and ten explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not fifteen;

the floating-point data elements are 16-bit floating-point data elements, having eight exponent bits, and seven explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not one hundred twenty seven;

the floating-point data elements are 8-bit floating-point data elements, having five exponent bits, and two explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not fifteen; and

the floating-point data elements are 8-bit floating-point data elements, having four exponent bits, and three explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not seven.

5 . The apparatus of claim 2 , wherein the exponent bias information is allowed to indicate any one of several different exponent biases to be used for the floating-point data elements.

6 . The apparatus of claim 1 , wherein the at least one value includes a first value of at least three bits and a second value of at least three bits, and wherein the first value and the second value are to indicate at least any two of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) a number of bits of the floating-point data elements; or (d) any combination thereof.

7 . The apparatus of claim 6 , wherein the floating-point data elements are 16-bit floating-point data elements, and wherein the first and second values are able to specify that the 16-bit floating-point data elements have any one of 3, 4, 5, 6, 7, 8, 9, or 10 exponent bits.

8 . The apparatus of claim 6 , wherein the floating-point data elements are 8-bit floating-point data elements, and wherein the first and second values are able to specify that the 8-bit floating-point data elements have any one of 3, 4, 5, or 6 exponent bits.

9 . The apparatus of claim 1 , wherein the at least one value includes a first value, a second value, and a third value, and wherein the first, second, and third values are to indicate at least any three of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; (d) a number of bits of the floating-point data elements; or (e) any combination thereof.

10 . The apparatus of claim 1 , wherein the at least one value is not part of an opcode of the instruction, and wherein the at least one value comprises at least four bits.

11 . The apparatus of claim 1 , further comprising a general-purpose register to store the at least one value, and wherein the instruction is to indicate the general-purpose register.

12 . The apparatus of claim 1 , further comprising a floating-point control register to store the at least one value.

13 . The apparatus of claim 1 , wherein the at least one value is part of an immediate.

14 . The apparatus of claim 1 , wherein the instruction is an add instruction, wherein the at least one source floating-point vector includes a first source floating-point vector that is to have the plurality of floating-point data elements and a second source floating-point vector that is to have a plurality of floating-point data elements, and wherein the execution circuitry, to perform the operation specified by the instruction on the at least one source floating-point vector, is to add corresponding floating-point data elements of the first and second source floating-point vectors to generate the result floating-point vector.

15 . The apparatus of claim 1 , wherein the instruction is a floating-point conversion instruction, wherein the at least one source floating-point vector includes a single source floating-point vector that is to have the plurality of floating-point data elements, and wherein the execution circuitry, to perform the operation specified by the instruction on the at least one source floating-point vector, is to convert the floating-point data elements of the single source floating-point vector to one of double precision, single precision, half precision, bfloat16, FP8 E5M2, or FP8 E4M3 floating-point data elements of the result floating-point vector.

16 . A method comprising:

decoding an instruction, the instruction indicating at least one source floating-point vector, a destination storage location, and at least one value, the source floating-point vector having a plurality of floating-point data elements, the at least one value indicating at least one of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; or (d) any combination thereof; and

performing operations according to the instruction, including:

interpreting the floating-point data elements consistent with the at least one value;

performing an operation specified by the instruction on the at least one source floating-point vector to generate a result floating-point vector; and

storing the result floating-point vector in the destination storage location.

17 . The method of claim 16 , wherein the at least one value is to indicate at least the exponent bias information, and wherein the exponent bias information is either to explicitly specify an exponent bias or an exponent bias offset.

18 . The method of claim 16 , wherein the at least one value includes a first value of at least three bits and a second value of at least three bits, and wherein the first value and the second value are to indicate at least any two of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) a number of bits of the floating-point data elements; or (d) any combination thereof.

19 . A system comprising:

an interconnect;

a processor coupled with the interconnect, the processor to receive an instruction, the instruction to indicate at least one source floating-point vector, a destination storage location, and at least one value, the source floating-point vector to have a plurality of floating-point data elements, the at least one value to indicate at least one of (a) a number of significand bits of the floating-point data elements, (b) a number of exponent bits of the floating-point data elements, (c) exponent bias information for the floating-point data elements, or (d) any combination thereof, the processor to perform operations according to the instruction, including to:

interpret the floating-point data elements consistent with the at least one value;

perform an operation specified by the instruction on the at least one source floating-point vector to generate a result floating-point vector; and

store the result floating-point vector in the destination storage location; and

a dynamic random access memory (DRAM) coupled with the interconnect.

20 . The system of claim 19 , wherein the at least one value is to indicate at least the exponent bias information, and wherein the exponent bias information is either to explicitly specify an exponent bias or an exponent bias offset.