Technologies for memory margin aware reliable software execution

1. A computing device for reliable software execution, the computing device comprising:

a memory that includes a plurality of ranks;

a memory initializer to train the plurality of ranks of the memory;

a rank margining tool to determine a consolidated memory score for each rank of the plurality of ranks in response to training of the plurality of ranks, wherein each consolidated memory score is indicative of a margin of the corresponding rank; and

a boot loader to (i) identify a higher-margin memory address range with the consolidated memory scores, wherein the higher-margin memory address range is mapped to a higher-margin memory rank, and (ii) load a high-priority software component into the higher-margin memory address range.

2. The computing device of claim 1 , wherein to determine the consolidated memory score comprises to determine a timing margin and to determine a voltage margin for the corresponding rank.

3. The computing device of claim 2 , wherein to determine the consolidated memory score comprises to:

determine a margin range vector, wherein each element of the margin range vector comprises a normalized margin value; and

determine a weighted average of the elements of the margin range vector.

4. The computing device of claim 1 , wherein the computing device further comprises a pre-boot firmware environment that establishes the memory initializer and the rank margining tool.

5. The computing device of claim 4 , wherein the rank margining tool is further to publish the plurality of consolidated memory scores to a higher-level software component of the computing device.

6. The computing device of claim 4 , further comprising an operating system;

wherein the pre-boot firmware environment further comprises the boot loader; and

the boot loader is to load the operating system into the higher-margin memory address range.

7. The computing device of claim 6 , wherein:

the boot loader is further to map the higher-margin memory address range to the higher-margin memory rank, wherein the higher-margin memory address range comprises a predetermined address range; and

to load the operating system comprises to load the operating system into the predetermined address range in response to mapping of the higher-margin memory address range to the higher-margin memory rank.

8. The computing device of claim 6 , further comprising a runtime loader to:

identify the higher-margin memory address range with the consolidated memory scores in response to loading of the operating system; and

load a second high-priority software component into the higher-margin memory address range;

wherein the operating system is to establish the runtime loader.

9. The computing device of claim 8 , wherein to identify the higher-margin memory address range comprises to access the plurality of consolidated memory scores published by the pre-boot firmware environment.

10. The computing device of claim 8 , wherein to load the second high-priority software component comprises to load a kernel data structure, a kernel module, or a kernel-mode driver into the higher-margin memory address range.

11. The computing device of claim 8 , further comprising:

a user-mode application; and

a scheduler to execute the user-mode application, wherein the scheduler is established by the operating system;

wherein the user-mode application is to request the operating system to load the user-mode application to a higher-margin memory address range in response to execution of the user-mode application; and

wherein to load the second high-priority software component comprises to load the user-mode application into the higher-margin memory address range in response to a request for the operating system to load the user-mode application.

12. A method for reliable software execution, the method comprising:

training, by a computing device, a plurality of ranks of a memory of the computing device;

determining, by the computing device, a consolidated memory score for each rank of the plurality of ranks in response to training the plurality of ranks, wherein each consolidated memory score is indicative of a margin of the corresponding rank;

identifying, by the computing device, a higher-margin memory address range using the consolidated memory scores, wherein the higher-margin memory address range is mapped to a higher-margin memory rank; and

loading, by the computing device, a high-priority software component into the higher-margin memory address range.

13. The method of claim 12 , wherein determining the consolidated memory score comprises determining a timing margin and determining a voltage margin for the corresponding rank.

14. The method of claim 12 , wherein:

training the plurality of ranks of the memory device comprises training the plurality of ranks of the memory by a pre-boot firmware environment of the computing device; and

determining the consolidated memory score for each rank comprises determining the consolidated memory score for each rank by the pre-boot firmware environment.

15. The method of claim 14 , further comprising publishing, by the pre-boot firmware environment, the plurality of consolidated memory scores to a higher-level software component of the computing device.

16. The method of claim 14 , wherein loading the high-priority software component into the higher-margin memory address range comprises loading, by the pre-boot firmware environment, an operating system into the higher-margin memory address range.

17. The method of claim 16 , further comprising:

mapping, by the pre-boot firmware environment, the higher-margin memory address range to the higher-margin memory rank, wherein the higher-margin memory address range comprises a predetermined address range;

wherein loading the operating system comprises loading the operating system into the predetermined address range in response to mapping the higher-margin memory address range to the higher-margin memory rank.

18. The method of claim 16 , further comprising:

identifying, by the operating system, the higher-margin memory address range using the consolidated memory scores in response to loading the operating system; and

loading, by the operating system, a second high-priority software component into the higher-margin memory address range.

19. One or more non-transitory, computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:

train a plurality of ranks of a memory of the computing device;

determine a consolidated memory score for each rank of the plurality of ranks in response to training the plurality of ranks, wherein each consolidated memory score is indicative of a margin of the corresponding rank;

identify a higher-margin memory address range using the consolidated memory scores, wherein the higher-margin memory address range is mapped to a higher-margin memory rank; and

load a high-priority software component into the higher-margin memory address range.

20. The one or more non-transitory, computer-readable storage media of claim 19 , wherein to determine the consolidated memory score comprises to determine a timing margin and determine a voltage margin for the corresponding rank.

21. The one or more non-transitory, computer-readable storage media of claim 19 , wherein:

to train the plurality of ranks of the memory device comprises to train the plurality of ranks of the memory by a pre-boot firmware environment of the computing device; and

to determine the consolidated memory score for each rank comprises to determine the consolidated memory score for each rank by the pre-boot firmware environment.

22. The one or more non-transitory, computer-readable storage media of claim 21 , further comprising a plurality of instructions that in response to being executed cause the computing device to publish, by the pre-boot firmware environment, the plurality of consolidated memory scores to a higher-level software component of the computing device.

23. The one or more non-transitory, computer-readable storage media of claim 21 , wherein to load the high-priority software component into the higher-margin memory address range comprises to load, by the pre-boot firmware environment, an operating system into the higher-margin memory address range.

24. The one or more non-transitory, computer-readable storage media of claim 23 , further comprising a plurality of instructions that in response to being executed cause the computing device to:

map, by the pre-boot firmware environment, the higher-margin memory address range to the higher-margin memory rank, wherein the higher-margin memory address range comprises a predetermined address range;

wherein to load the operating system comprises to load the operating system into the predetermined address range in response to mapping the higher-margin memory address range to the higher-margin memory rank.

25. The one or more non-transitory, computer-readable storage media of claim 23 , further comprising a plurality of instructions that in response to being executed cause the computing device to:

identify, by the operating system, the higher-margin memory address range using the consolidated memory scores in response to loading the operating system; and

load, by the operating system, a second high-priority software component into the higher-margin memory address range.