DYNAMIC MEMORY OFFLINING AND VOLTAGE SCALING
An embodiment of a semiconductor package apparatus may include technology to independently bring a first memory power node one of online and offline based on a runtime memory control signal, and independently bring a second memory power node one of online and offline based on the runtime memory control signal. Other embodiments are disclosed and claimed.
1 . A system, comprising:
a first memory power node including a first set of one or more memory devices;
a first power source coupled to the first memory power node;
a second memory power node including a second set of one or more memory devices;
a second power source coupled to the second memory power node; and
logic coupled to the first memory power node and the second memory power node, the logic to:
independently bring the first memory power node one of online and offline based on a runtime memory control signal, and
independently bring the second memory power node one of online and offline based on the runtime memory control signal.
2 . The system of claim 1 , wherein the logic is further to:
scale a voltage provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
3 . The system of claim 1 , wherein the logic is further to:
scale an operating frequency provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
4 . The system of claim 1 , wherein the runtime memory control signal is based on a memory power state.
5 . The system of claim 1 , wherein the memory devices include non-volatile memory devices.
6 . The system of claim 1 , wherein the first power source is coupled to the first memory power node with a first voltage rail, and wherein the second power source is coupled to the second memory power node with a second voltage rail.
7 . An apparatus, comprising:
a substrate; and
logic coupled to the substrate, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the substrate to:
independently bring a first memory power node one of online and offline based on a runtime memory control signal, and
independently bring a second memory power node one of online and offline based on the runtime memory control signal.
8 . The apparatus of claim 7 , wherein the logic is further to:
scale a voltage provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
9 . The apparatus of claim 7 , wherein the logic is further to:
scale an operating frequency provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
10 . The apparatus of claim 7 , wherein the runtime memory control signal is based on a memory power state.
11 . The apparatus of claim 7 , wherein the first and second memory power nodes each include one or more non-volatile memory devices.
12 . The apparatus of claim 7 , wherein the first memory power node is coupled to a first voltage rail, and wherein the second memory power node is coupled to a second voltage rail.
13 . A method comprising:
independently bringing a first memory power node one of online and offline based on a runtime memory control signal; and
independently bringing a second memory power node one of online and offline based on the runtime memory control signal.
14 . The method of claim 13 , further comprising:
scaling a voltage provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
15 . The method of claim 13 , further comprising:
scaling an operating frequency provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
16 . The method of claim 13 , wherein the runtime memory control signal is based on a memory power state.
17 . The method of claim 13 , further comprising:
providing one or more non-volatile memory devices for each of the first and second memory power nodes.
18 . The method of claim 13 , further comprising:
coupling the first memory power node to a first voltage rail; and
coupling the second memory power node to a second voltage rail.
19 . At least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
independently bring a first memory power node one of online and offline based on a runtime memory control signal; and
independently bring a second memory power node one of online and offline based on the runtime memory control signal.
20 . The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
scale a voltage provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
21 . The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
scale an operating frequency provided to one or more of the first and second memory power nodes based on the runtime memory control signal.
22 . The at least one computer readable medium of claim 19 , wherein the runtime memory control signal is based on a memory power state.
23 . The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
provide one or more non-volatile memory devices for each of the first and second memory power nodes.
24 . The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
couple the first memory power node to a first voltage rail; and
couple the second memory power node to a second voltage rail.