Virtual Platforms of Integrated Circuit Designs
Systems or methods of the present disclosure may provide receiving configuration data corresponding to a circuit design for programmable logic circuitry. A first intellectual property (IP) block is configured using parameterization data of the configuration data. A stub model is generated for a second IP block using interconnect and register data of the configuration data. A chip-level model is generated that represents the circuit design based on the first IP block, the stub model, and memory map data of the configuration data. The chip-level model is consumable by a virtual platform simulator.
1 . A method comprising:
receiving configuration data corresponding to a circuit design for programmable logic circuitry;
configuring a first intellectual property (IP) block using parameterization data of the configuration data;
generating a stub model for a second IP block using interconnect and register data of the configuration data; and
generating a chip-level model that represents the circuit design based on the first IP block, the stub model, and memory map data of the configuration data, wherein the chip-level model is consumable by a virtual platform simulator.
2 . The method of claim 1 , comprising generating a platform-level model based on the chip-level model and external connectivity data of the configuration data.
3 . The method of claim 1 , comprising providing the chip-level model to the virtual platform simulator.
4 . The method of claim 1 , wherein generating the stub model comprises generating a wrapper that includes implementation code that characterizes parameters of the second IP block.
5 . The method of claim 1 , wherein the chip-level model instantiates a chip-level memory map that characterizes connectivity between the first IP block and the stub model.
6 . The method of claim 1 , wherein the chip-level model is configured to execute a software binary that is executable by an implementation of the circuit design on the programmable logic circuitry.
7 . The method of claim 1 , wherein the first IP block is available in a design tool library of vendor IP blocks, and the second IP block is unavailable in the design tool library.
8 . The method of claim 1 , wherein a hierarchy of the chip-level model conforms to a hierarchy of a register-transfer level (RTL) model characterizing the circuit design.
9 . A tangible, non-transitory, computer-readable medium, comprising instructions that, when executed by a processor, cause operations to be performed comprising:
receiving configuration data corresponding to a circuit design for programmable logic circuitry;
generating a stub model for an intellectual property (IP) block using interconnect and register data of the configuration data;
generating a chip-level model that represents the circuit design based on the stub model, and memory map data of the configuration data; and
executing a software binary that is executable by an implementation of the circuit design on the programmable logic circuitry using the chip-level model.
10 . The tangible, non-transitory, computer-readable medium of claim 9 , wherein the software binary comprises a bootloader, an operating system, low-level firmware, middleware, a library, software development kit, an application programming interface, or a combination thereof.
11 . The tangible, non-transitory, computer-readable medium of claim 9 , the operations comprising generating a platform-level model based on the chip-level model and external connectivity data of the configuration data.
12 . The tangible, non-transitory, computer-readable medium of claim 11 , wherein the external connectivity data comprises input/output (I/O) pin assignments of a board-level component.
13 . The tangible, non-transitory, computer-readable medium of claim 9 , wherein the memory map data includes information for integrating the implementation of the circuit design on the programmable logic circuitry with a board-level component.
14 . The tangible, non-transitory, computer-readable medium of claim 9 , wherein the memory map data defines an association between a register map of the stub model and another register map.
15 . An electronic device comprising:
a processor; and
memory coupled to the processor, the memory storing instructions which, when executed by the processor, cause the processor to:
receive configuration data corresponding to a circuit design for programmable logic circuitry;
generate a bitstream based on the configuration data;
generate a stub model for an intellectual property (IP) block using interconnect and register data of the configuration data; and
output the bitstream to the programmable logic circuitry and the stub model to a simulator application.
16 . The electronic device of claim 15 , the memory storing instructions which, when executed by the processor, cause the processor to:
generate a platform-level model based on the stub model and external connectivity data of the configuration data.
17 . The electronic device of claim 15 , the memory storing instructions which, when executed by the processor, cause the processor to:
execute a software binary that is executable by an implementation of the circuit design on the programmable logic circuitry.
18 . The electronic device of claim 15 , wherein the memory map data defines an association between a register map of the stub model and a system-level map.
19 . The electronic device of claim 15 , wherein the IP block is unavailable in a design tool library of vendor IP blocks.
20 . The electronic device of claim 19 , the memory storing instructions which, when executed by the processor, cause the processor to:
receive a vendor IP block from the design tool library; and
configure the vendor IP block using parameterization data of the configuration data.