IP Library Granted Patent US 12,381,179
Granted Patent B2
US 12,381,179 · App. 17/693,005 · Granted Aug 5, 2025

Modular low latency electrical sequence for die-to-die interface

Inventors: Phaik Yi Chan (Bayan Lepas, MY); Ting Ting Teh (San Jose, CA)
Assignee: Intel Corporation
H01L25/0652H01L2225/06513
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Quick Facts
Patent No.
US 12,381,179
App. No.
17/693,005
Granted
Aug 5, 2025
Kind
B2
Abstract

A system comprising a first die comprising a first receiver and a first transmitter to couple to a link between the first die and a second die comprising a second receiver and a second transmitter; and circuitry to place the first receiver and first transmitter into isolation modes; provide a first signal to the second die to request placement of the second transmitter into a deisolation mode; place the first receiver and first transmitter into deisolation modes responsive to a second signal from the second die; and provide a third signal to the second die to request placement of the second receiver into a deisolation mode.

Claims (46)

1. A system comprising:

a first die in a package, the first die comprising:

a first receiver and a first transmitter to couple to a link between the first die and a second die in the package, the second die comprising a second receiver and a second transmitter; and

circuitry to:

place the first receiver and first transmitter into isolation modes;

provide a first signal to the second die to request placement of the second transmitter into a deisolation mode;

place the first receiver and first transmitter into deisolation modes responsive to a second signal from the second die; and

provide a third signal to the second die to request placement of the second receiver into a deisolation mode.

2. The system of claim 1 , wherein:

the first signal is sent over a first wire dedicated to the first signal;

the second signal is sent over a second wire dedicated to the second signal; and

the third signal is sent over a third wire dedicated to the third signal.

3. The system of claim 2 , further comprising the first wire, second wire, and third wire.

4. The system of claim 3 , further comprising the second die.

5. The system of claim 4 , wherein the first die comprises a processor to generate data to be communicated over the link.

6. The system of claim 5 , further comprising a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

7. The system of claim 1 , wherein placing the first receiver into an isolation mode comprises driving an output of the receiver to a fixed logical value.

8. The system of claim 1 , wherein placing the first transmitter into an isolation mode comprises driving an output of the transmitter to a low voltage value.

9. The system of claim 1 , wherein placing the first receiver into a deisolation mode comprises configuring the first receiver to output an output of the second transmitter.

10. The system of claim 1 , wherein placing the first transmitter into a deisolation mode comprises configurating the first transmitter to output an output of a protocol layer of the first die.

11. The system of claim 1 , wherein the circuitry is, during a power off flow, to:

transition the first receiver from a deisolation mode to an isolation mode;

transition the first signal to request placement of the second receiver and second transmitter into isolation modes; and

transition the first transmitter from a deisolation mode to an isolation mode responsive to a transition of the second signal.

12. The system of claim 11 , wherein the circuitry is to power off the first receiver and the first transmitter after transitioning the first transmitter to the isolated mode.

13. The system of claim 1 , wherein the first die comprises a central processing unit or graphics processing unit and the second die comprises a system on a die.

14. An apparatus comprising:

a first die in a package, the first die comprising:

a first receiver and a first transmitter to couple to a link between the first die and a second die in the package, the second die comprising a second receiver and a second transmitter; and

circuitry to:

place the first transmitter into an isolation mode when the second receiver is to be powered down; and

place the first receiver into an isolation mode when the second transmitter is to be powered down.

15. The apparatus of claim 14 , wherein placing the first transmitter into the isolation mode comprises driving the output of the first transmitter to a low voltage.

16. The apparatus of claim 14 , wherein placing the first receiver into the isolation mode comprises driving the output of the first receiver to a fixed logical value.

17. The apparatus of claim 14 , wherein the circuitry is to transition a first signal to request isolation or deisolation of the second receiver and the second transmitter.

18. The apparatus of claim 14 , wherein the circuitry is to transition the first receiver and the first transmitter to deisolation modes responsive to a signal received from the second die.

19. An apparatus comprising:

circuitry to bring up a link between a first die in a package and a second die in the package, wherein bringing up the link comprises:

isolating a first transmitter and a first receiver of the first die and a second transmitter and a second receiver of the second die;

deisolating the second transmitter while the first receiver is still isolated;

deisolating the first receiver and the first transmitter while the second receiver is still isolated; and

deisolating the second receiver after the first receiver and the first transmitter are deisolated.

20. The apparatus of claim 19 , the circuitry further to take down the link, wherein taking down the link comprises:

isolating the first receiver;

isolating the second receiver and the second transmitter after isolating the first receiver; and

isolating the first transmitter after isolating the second receiver and the second transmitter.

Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 072704/0307 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2022
From: CHAN, PHAIK YI; TEH, TING TING
To: INTEL CORPORATION
Reel/Frame 059246/0485 →
Continuity (1)
Related Publication 20220199573A1 · Jun 23, 2022
References Cited (5)
US 20190068397A1 · Chen · 2019 [cited by examiner]
US 20200098621A1 · Bharath · 2020 [cited by examiner]
US 20220319569A1 · Veches · 2022 [cited by examiner]
US 20230268637A1 · Dutta · 2023 [cited by examiner]
EPO Extended European Search Report in EP Application Serial No. 23151127.0 mailed on Jul. 14, 2023 (10 pages). [cited by applicant]