IP Library Granted Patent US 9,971,567
Granted Patent B2
US 9,971,567 · App. 15/390,715 · Granted May 15, 2018

Method and apparatus for randomizer

Inventors: Michael J. Miller (Saratoga, CA); Michael J. Morrison (Sunnyvale, CA); Jay B Patel (Los Gatos, CA)
Assignee: MoSys, Inc.
G06F7/582
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Quick Facts
Patent No.
US 9,971,567
App. No.
15/390,715
Granted
May 15, 2018
Kind
B2
Abstract

The randomizer includes connection circuitry with a random connection layout to parallely couple each of a quantity of bits for each of a plurality of inputs of bit width n to multiple output bits of a respectively coupled output. Combinational circuitry combines at least a portion of each of the plurality of outputs associated with each of the plurality of inputs to create a single resultant output of random data having a bit width of the quantity n.

Claims (71)

1. An apparatus for randomizing input data comprising;

a plurality of inputs, each having a data input bit width of quantity n, where n equals a positive integer;

a plurality of outputs, each respectively coupled to one of the plurality of inputs; and

connection circuitry coupled to the plurality of outputs;

combinational circuitry coupled to the plurality of outputs; and wherein:

each of the quantity n bits of a given data input is parallely coupled by the connection circuitry in a random connection layout to a quantity x of output bits in the respectively coupled output; and

each of the plurality of outputs is grouped into a quantity of bit groups equal to the quantity n, with each bit group having a bit-width of the quantity x; and

the combinational logic combines at least a portion of each of the plurality of outputs to create a single resultant output of random data having a bit width of the quantity n.

2. The apparatus of claim 1 wherein:

the combinatorial logic is an XOR device.

3. The apparatus of claim 1 wherein:

the random connection layout coupling each of the quantity of n bits of the given data input to the plurality of output bits in the respectively coupled output is predetermined.

4. The apparatus of claim 1 wherein:

the random connection layout coupling each of the quantity of n bits of the given data input to the plurality of output bits in the respectively coupled output lacks any structure or pattern.

5. The apparatus of claim 1 wherein:

the random connection layout coupling each of the quantity of n bits of the given data input to the plurality of output bits in the respectively coupled output does not couple consecutive inputs to output pairs with the same exact relative pattern.

6. The apparatus of claim 1 further comprising:

an input signal coupled to the plurality of inputs and the plurality of outputs; and wherein:

the input signal selects one of a plurality of variations of the random connection layout.

7. The apparatus of claim 1 further comprising:

a data source coupled to at least one of the plurality of inputs; and wherein:

the data source provides only consistent logic values to the at least one of the plurality of inputs with bit width of quantity n; and

the consistent logic values do not change while the apparatus is in operation.

8. The apparatus of claim 1 further comprising:

a data source of any consistent logic values that is not changing; and wherein:

at least one of the plurality of inputs with bit width of quantity n is provided by the data source.

9. The apparatus of claim 1 wherein:

two of the plurality of inputs is a same data set having the bit width of quantity n.

10. The apparatus of claim 1 further comprising;

a first plurality of inputs coupled to a first plurality of outputs via a first random connection layout; and

a second plurality of inputs coupled to a second plurality of outputs via a second random connection layout; and wherein:

the first random connection layout is different from the second random connection layout.

11. A system for randomizing data comprising;

a plurality of apparatus for randomizing input data coupled to each other in series; and

wherein:

each of the plurality of apparatus comprises:

a plurality of inputs, each having a data input bit width of quantity n, where n equals a positive integer;

a plurality of outputs, each respectively coupled to one of the plurality of inputs; and

connection circuitry coupled to the plurality of outputs;

combinational circuitry coupled to the plurality of outputs; and wherein:

each of the quantity n bits of a given data input is parallely coupled by the connection circuitry in a random connection layout to a quantity x of output bits in the respectively coupled output; and

each of the plurality of outputs is grouped into a quantity of bit groups equal to the quantity n, with each bit group having a bit-width of the quantity x; and

the combinational logic combines at least a portion of each of the plurality of outputs to create a single resultant output of random data having a bit width of the quantity n.

12. A method for randomizing data comprising;

receiving a plurality of inputs at an apparatus for randomizing input data, each having a data input bit width of quantity n, where n equals a positive integer;

routing each of the plurality of inputs to a plurality of outputs via a connection circuitry; and wherein:

each of the quantity n bits of a given data input is parallely coupled by the connection circuitry in a random connection layout to a quantity x of output bits in the respectively coupled output; and

each of the plurality of outputs is grouped into a quantity of bit groups equal to the quantity n, with each bit group having a bit-width of the quantity x; and

at least a portion of each of the plurality of outputs is combined via a combinational circuit to create a single resultant output of random data having a bit width of the quantity n.

13. The system for randomizing data of claim 11 wherein:

for each of the plurality of apparatus, the random connection layout coupling each of the quantity of n bits of the given data input to the plurality of output bits in the respectively coupled output is predetermined.

14. The system for randomizing data of claim 11 wherein:

for each of the plurality of apparatus, the random connection layout coupling each of the quantity of n bits of the given data input to the plurality of output bits in the respectively coupled output lacks any structure or pattern.

15. The system for randomizing data of claim 11 wherein:

for each of the plurality of apparatus, the random connection layout coupling each of the quantity of n bits of the given data input to the plurality of output bits in the respectively coupled output does not couple consecutive inputs to output pairs with the same exact relative pattern.

16. The system for randomizing data of claim 11 wherein:

each of the plurality of apparatus further comprises:

an input signal coupled to the plurality of inputs and the plurality of outputs; and wherein:

the input signal selects one of a plurality of variations of the random connection layout.

17. The system for randomizing data of claim 11 wherein:

each of the plurality of apparatus further comprises:

a data source coupled to at least one of the plurality of inputs; and wherein:

the data source provides only consistent logic values to the at least one of the plurality of inputs with bit width of quantity n; and

the consistent logic values do not change while the apparatus is in operation, for each of the respective plurality of apparatus.

18. The method of claim 12 wherein:

consecutive inputs are not coupled to consecutive output pairs with the same exact relative pattern.

19. The method of claim 12 , further comprising:

receiving a consistent logic value from a data source coupled to at least one of the plurality of inputs with bit width of quantity n; and

the consistent logic values do not change while the apparatus is in operation.

20. The method of claim 12 wherein:

two of the plurality of inputs is a same data set having the bit width of quantity n.

Assignments (5)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 072704/0307 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2022
From: PERASO, INC.
To: INTEL CORPORATION
Reel/Frame 061586/0847 →
CHANGE OF NAME Recorded Sep 27, 2022
From: MOSYS, INC.
To: PERASO INC.
Reel/Frame 061541/0542 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2016
From: MILLER, MICHAEL J; MORRISON, MICHAEL J; PATEL, JAY B
To: MOSYS, INC.
Reel/Frame 040766/0521 →
Continuity (4)
Continuation 14839576 · Aug 28, 2015
Continuation PCTUS2014072870 · Dec 30, 2014
Provisional Application 61922592 · Dec 31, 2013
Related Publication 20170109135A1 · Apr 20, 2017