IP Library Granted Patent US 12,436,413
Granted Patent B2
US 12,436,413 · App. 17/710,703 · Granted Oct 7, 2025

Undercut design with a bonded base cover for friendly assembly and effective thermal tuning of micro-ring resonator (MRR) in open cavity photonic integrated chips (OCPIC)

Inventors: Chia-Pin Chiu (Tempe, AZ); Kaveh Hosseini (Livermore, CA); Omkar Karhade (Chandler, AZ); Tim Tri Hoang (San Jose, CA)
Assignee: Intel Corporation
G02F1/0147G02B6/29395G02B6/2934G02F2203/15
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Quick Facts
Patent No.
US 12,436,413
App. No.
17/710,703
Granted
Oct 7, 2025
Kind
B2
Abstract

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

Claims (42)

1. An optoelectronic system, comprising:

a first substrate;

a second substrate over the first substrate;

a micro-ring resonator (MRR) over the second substrate;

a heater integrated into the MRR;

a cladding over the MRR;

an opening through the first substrate and the second substrate to expose a bottom surface of the MRR; and

a base spanning across the opening.

2. The optoelectronic system of claim 1 , wherein the first substrate comprises silicon and the second substrate comprises an oxide.

3. The optoelectronic system of claim 1 , wherein the opening continues into the cladding adjacent to sidewalls of the MRR.

4. The optoelectronic system of claim 3 , wherein the opening continues into the cladding past a top surface of the MRR.

5. The optoelectronic system of claim 1 , wherein the base comprises silicon.

6. The optoelectronic system of claim 1 , wherein the base comprises glass.

7. The optoelectronic system of claim 1 , wherein a thickness of the base is greater than a thickness of the first substrate.

8. The optoelectronic system of claim 1 , wherein the opening through the first substrate has substantially vertical sidewalls.

9. The optoelectronic system of claim 1 , wherein the opening through the first substrate has tapered sidewalls.

10. The optoelectronic system of claim 1 , further comprising:

contacts coupled to a top surface of the MRR.

11. The optoelectronic system of claim 10 , wherein the contacts are electrically coupled to pads on a top surface of the cladding.

12. The optoelectronic system of claim 1 , wherein the MRR has a thickness that is approximately 250 nm or less.

13. A method of forming an optoelectronic system, comprising:

forming a micro-ring resonator (MRR) with a heater on a substrate, wherein the substrate is a silicon on insulator (SOI) substrate with a silicon substrate and an oxide layer over the silicon substrate, and wherein a cladding is provided over and around the MRR;

applying a mask to a bottom surface of the silicon substrate, wherein an opening of the mask is aligned with the MRR;

etching through the silicon substrate and the oxide layer to expose a bottom surface of the MRR; and

attaching a base to the silicon substrate that spans across a hole in the silicon substrate.

14. The method of claim 13 , wherein a width of the opening of the mask is wider than a width of the MRR.

15. The method of claim 14 , wherein the etching further comprises etching the cladding adjacent to the MRR.

16. The method of claim 15 , wherein the etching of the cladding extends past a top surface of the MRR.

17. The method of claim 13 , wherein the base comprises silicon or glass.

18. An optoelectronic system, comprising:

a package substrate;

a photonics integrated circuit (PIC) coupled to the package substrate, wherein the PIC comprises:

a first substrate;

a second substrate over the first substrate;

a micro-ring resonator (MRR) over the second substrate;

a heater integrated into the MRR;

a cladding over the MRR;

an opening through the first substrate and the second substrate to expose a bottom surface of the MRR; and

a base spanning across the opening; and

an electronic integrated circuit (EIC) coupled to the PIC.

19. The optoelectronic system of claim 18 , wherein the base comprises glass.

20. The optoelectronic system of claim 18 , wherein the base comprises silicon.

Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 072704/0307 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2023
From: CHIU, CHIA-PIN; HOSSEINI, KAVEH; KARHADE, OMKAR; HOANG, TIM TRI
To: INTEL CORPORATION
Reel/Frame 064249/0807 →
Continuity (1)
Related Publication 20230314849A1 · Oct 5, 2023
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