Diagnostic testing of FPGAs for safety critical systems
Methods and apparatus relating to diagnostic testing of FPGAs for safety critical systems are described. In an embodiment, logic circuitry (e.g., a processor) performs one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors. Memory stores the one or more test vectors. The logic circuitry performs the one or more diagnostic operations on the portion of the FPGA during runtime. Other embodiments are also disclosed and claimed.
1. An apparatus comprising:
logic circuitry to perform one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors; and
memory to store the one or more test vectors,
wherein the logic circuitry is to perform the one or more diagnostic operations on the portion of the FPGA during runtime, wherein a vehicle comprises the logic circuitry and the memory.
2. The apparatus of claim 1 , wherein the portion of the FPGA comprises core programmable logic.
3. The apparatus of claim 1 , wherein the portion of the FPGA excludes programmable input and output pins and fixed function circuits.
4. The apparatus of claim 1 , wherein the one or more diagnostic operations are to check for one or more of: a stuck-at fault error, a clock fault error, a Logic Element (LE) configuration error, and a routing configuration error.
5. The apparatus of claim 1 , wherein the portion of the FPGA comprises core programmable logic, wherein diagnostic testing of the core programmable logic includes a development operation and a deployment operation.
6. The apparatus of claim 5 , wherein the development operation comprises:
completion of a design using an FPGA implementation tool, locking of design features, application of one or more Design For Test (DFT) operations to generate a diagnostic design, and deployment of both the one or more test vectors and the diagnostic design.
7. The apparatus of claim 6 , wherein the locking of the design features comprises locking: logic placement, signal routing, and clock routing.
8. The apparatus of claim 6 , wherein the locking of the design features is to indicate that the design is a runtime design.
9. The apparatus of claim 6 , wherein the one or more DFT operations are to provide the one or more test vectors.
10. The apparatus of claim 5 , wherein the deployment operation comprises: receipt of a request to perform a diagnostic test on the portion of the FPGA, loading of an FPGA diagnostic design, application of the one or more test vectors, reading results of the application, and reloading the FPGA with a runtime design in response to an indication by the results that the FPGA has passed diagnostics test, and logging of an event in response to an indication by the results that the FPGA has failed the diagnostics test.
11. The apparatus of claim 1 , wherein a System On Chip (SOC) device or a signal integrated circuit device comprises one or more of: the logic circuitry, the memory, and a processor having one or more processor cores.
12. The apparatus of claim 1 , wherein an Internet of Things (IoT) device comprise one or more of: the logic circuitry, the memory, and a processor having one or more processor cores.
13. The apparatus of claim 1 , wherein the vehicle comprises one or more of: an automobile, a truck, a motorcycle, an airplane, a helicopter, a vessel or ship, a train, or a drone.
14. One or more non-transitory computer-readable medium comprising one or more instructions that, when executed on at least one processor, configure the at least one processor to perform one or more operations to:
perform one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors; and
cause storage of the one or more test vectors in memory,
wherein the at least one processor is to perform the one or more diagnostic operations on the portion of the FPGA during runtime, wherein a vehicle comprises the logic circuitry and the memory.
15. The one or more non-transitory computer-readable medium of claim 14 , wherein the portion of the FPGA comprises core programmable logic.
16. The one or more non-transitory computer-readable medium of claim 14 , wherein the one or more diagnostic operations comprise one or more of: a stuck-at fault error, a clock fault error, a Logic Element (LE) configuration error, and a routing configuration error.
17. The one or more non-transitory computer-readable medium of claim 14 , wherein the portion of the FPGA comprises core programmable logic, wherein diagnostic testing of the core programmable logic includes a development operation and a deployment operation.
18. The one or more non-transitory computer-readable medium of claim 17 , wherein the development operation comprises: completion of a design using an FPGA implementation tool, locking of design features, application of one or more Design For Test (DFT) operations to generate a diagnostic design, and deployment of both the one or more test vectors and the diagnostic design for field operation.
19. The one or more non-transitory computer-readable medium of claim 17 , wherein the deployment operation comprises: receipt of a request to perform a diagnostic test on the portion of the FPGA, loading of an FPGA diagnostic design, application of the one or more test vectors, reading results of the application, and reloading the FPGA with a runtime design in response to an indication by the results that the FPGA has passed diagnostics test, and logging of an event in response to an indication by the results that the FPGA has failed the diagnostics test.
20. The one or more non-transitory computer-readable medium of claim 14 , wherein the vehicle comprises one or more of: an automobile, a truck, a motorcycle, an airplane, a helicopter, a vessel or ship, a train, or a drone.