Integrated circuits with complementary non-volatile resistive memory elements
View Patent ↗Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.
1. An integrated circuit comprising:
a first power supply terminal that receives a first adjustable power supply voltage;
a second power supply terminal that receives a second adjustable power supply voltage;
a first non-volatile resistive element that comprises:
a first anode terminal coupled to the first power supply terminal; and
a first cathode terminal; and
a second non-volatile resistive element that comprises:
a second anode terminal coupled to the second power supply terminal; and
a second cathode terminal coupled to the first cathode terminal of the first non-volatile resistive element, wherein the first non-volatile resistive element and the second non-volatile resistive element form a conductive-bridging random-access memory cell.
2. The integrated circuit of claim 1 , further comprising:
a first tristate buffer that drives the first power supply terminal; and
a second tristate buffer that drives the second power supply terminal.
3. The integrated circuit of claim 1 , wherein the first adjustable power supply voltage is negative.
4. The integrated circuit of claim 1 , wherein the second adjustable power supply voltage is negative.
5. An integrated circuit comprising:
a first power supply terminal that receives a first adjustable power supply voltage;
a second power supply terminal that receives a second adjustable power supply voltage;
a first non-volatile resistive element that comprises:
a first anode terminal coupled to the first power supply terminal; and
a first cathode terminal; and
a second non-volatile resistive element that comprises:
a second anode terminal coupled to the second power supply terminal;
a second cathode terminal coupled to the first cathode terminal of the first non-volatile resistive element;
a data line;
an address transistor coupled between the data line and the first cathode terminal;
an additional power supply line;
a first transistor coupled between the additional power supply line and the data line, the first transistor receives a bias control voltage; and
a second transistor coupled in series with the first transistor between the additional power supply line and the data line, the second transistor receives a verification control voltage.
6. The integrated circuit of claim 1 , further comprising:
a pass transistor having a gate terminal that receives a static control signal from the first cathode terminal.
7. The integrated circuit of claim 1 , further comprising:
input-output circuitry having a first gate oxide thickness; and
an address transistor coupled to the first cathode terminal, the address transistor having a second gate oxide thickness that is less than the first gate oxide thickness.
8. A method of operating an integrated circuit, the method comprising:
driving a data line to a negative voltage level, wherein the integrated circuit includes a first non-volatile resistive element and a second non-volatile resistive element coupled in series between a first power supply line and a second power supply line, and wherein the first and second non-volatile resistive elements are coupled to the data line; and
programming the first non-volatile resistive element by driving the first power supply line to a positive voltage level while a cathode terminal of the first non-volatile resistive element receives the negative voltage level.
9. The method of claim 8 , wherein the magnitude of the negative voltage level and the magnitude of the positive voltage level are equal.
10. The method of claim 8 , further comprising:
erasing the second non-volatile resistive element by driving the data line to the positive voltage level while driving the second power supply line to the negative voltage level.
11. The method of claim 8 , wherein the first non-volatile resistive element has a first cathode terminal, and wherein the second non-volatile resistive element has a second cathode terminal that faces the first cathode terminal.
12. The method of claim 8 , further comprising configuring the second power supply line in a high impedance state.
13. The method of claim 8 , further comprising:
during a global erase operation, driving both the first and second power supply lines to the negative voltage level while driving the data line to the positive voltage level.
14. The method of claim 8 , further comprising:
determining whether the resistance of the second non-volatile resistive element is sufficiently low.