Low-skew channel bonding using phase-measuring FIFO buffer

1. A circuit for low-skew bonding of a plurality of data channels into a multi-lane data channel, the circuit comprising:

a plurality of phase-measuring first-in first-out buffer circuits which buffer a plurality of pre-buffer parallel data signals, output a plurality of buffered parallel data signals, and generate a plurality of phase-measurement signals which measure phases of the plurality of pre-buffer parallel data signals and provides a plurality of occupancy levels;

a plurality of transmission bit-slip circuits which receive a plurality of pre-slip parallel data signals and a plurality of bit-slip control signals and outputs a plurality of bit-slipped parallel data signals; and

a channel-bonding control circuit which receives the plurality of phase-measurement signals from the plurality of phase-measuring first-in first-out buffer circuits and provides the plurality of bit-slip control signal to the plurality of transmission bit-slip circuits, and determines a maximum occupancy level from the plurality of occupancy levels, and wherein a plurality of occupancy differences are computed from differences between the maximum occupancy level and each of the plurality of occupancy levels.

2. The circuit of claim 1 , wherein the plurality of transmission bit-slip circuits controllably delay the pre-slip parallel data signals by integral numbers of bits that are indicated by the plurality of bit-slip control signals received from the channel-bonding control circuit.

3. The circuit of claim 2 , further comprising:

a plurality of bypass register circuits which receive a plurality of input parallel data signals from a plurality of core registers and receive a plurality of bypass register control signals from the channel-bonding control circuit.

4. The circuit of claim 3 , wherein the plurality of bypass register circuits output a plurality of conditional parallel-delayed signals, wherein a conditional parallel-cycle delayed signal output by a bypass register circuit of the plurality of bypass register circuits is delayed by a parallel cycle when the bypass register circuit receives a bypass register control signal in a first state, and wherein the conditional parallel-cycle delayed signal output by the bypass register circuit is not delayed by a parallel cycle when the bypass register circuit receives the bypass register control signal in a second state.

5. The circuit of claim 3 , wherein the plurality of pre-buffer parallel data signals comprise the plurality of conditional parallel-cycle delayed signal that are output from the plurality of bypass register circuits.

6. The circuit of claim 3 , wherein the plurality of pre-slip parallel data signals comprise the plurality of conditional parallel-cycle delayed signals that are output from the plurality of bypass register circuits.

7. The circuit of claim 3 , further comprising:

a plurality of encoder circuits that receive a plurality of pre-encode parallel data signals and output a plurality of encoded parallel data signals.

8. The circuit of claim 7 , wherein the plurality of pre-encode parallel data signals comprise the plurality of buffered parallel data signals output from the plurality of phase-measuring first-in first-out buffer circuits, and wherein the plurality of encoded parallel data signals comprise the plurality of pre-slip parallel data signals that are input by the plurality of transmission bit-slip circuits.

9. The circuit of claim 7 , further comprising:

a plurality of serializer circuits that output a plurality of serial data signals of the multi-lane data channel, wherein the plurality of pre-encode parallel data signals comprise the plurality of buffered parallel data signals output from the plurality of phase-measuring first-in first-out buffer circuits, and wherein the plurality of encoded parallel data signals input by the plurality of serializer circuits.

10. The circuit of claim 2 , wherein each phase-measuring FIFO circuit of the plurality of phase-measuring FIFO circuits receives read and write enable signals, and wherein at least one of said enable signals are controlled to adjust a depth of the phase-measuring FIFO circuit.

11. The circuit of claim 1 , wherein a plurality of bit slip numbers are computed from the plurality of occupancy differences.

12. The circuit of claim 11 , wherein a bit slip number is reduced by a width of a parallel data signal when the bit slip number is greater than the width of the parallel data signal.

13. A method of low-skew bonding of a plurality of data channels into a multi-lane data channel, the method comprising:

buffering a plurality of pre-buffer parallel data signals by a plurality of phase-measuring first-in first-out buffer circuits;

outputting a plurality of buffered parallel data signals by the plurality of phase-measuring first-in first-out buffer circuits;

generating a plurality of phase-measurement signals by the plurality of phase-measuring first-in first-out buffer circuits, wherein the plurality of phase-measurement signals measure phases of the plurality of pre-buffer parallel data signals;

receiving a plurality of pre-slip parallel data signals and a plurality of bit-slip control signals by a plurality of transmission bit-slip circuits;

outputting a plurality of bit-slipped parallel data signals by the plurality of transmission bit-slip circuits;

receiving the plurality of phase-measurement signals by a channel-bonding control circuit; and

providing the plurality of bit-slip control signal from the channel-bonding control circuit to the plurality of transmission bit-slip circuits.

14. The method of claim 13 , further comprising:

delaying the plurality of pre-slip parallel data signals by integral numbers of bits that are indicated by the plurality of bit-slip control signals received by the plurality of transmission bit-slip circuits from the channel-bonding control circuit.

15. The method of claim 14 , further comprising:

receiving a plurality of input parallel data signals by a plurality of bypass register circuits;

receiving a plurality of bypass register control signals by the plurality of bypass register circuits from the channel-bonding control circuit; and

outputting a plurality of conditional parallel-delayed signals from the plurality of bypass register circuits.

16. The method of claim 15 , further comprising:

delaying a conditional parallel-cycle delayed signal output by a bypass register circuit by a parallel cycle when the bypass register circuit receives a bypass register control signal in a first state, and not delaying the conditional parallel-cycle delayed signal output by the bypass register circuit by the parallel cycle when the bypass register circuit receives the bypass register control signal in a second state.

17. The method of claim 13 , wherein the plurality of phase-measurement signals provides a plurality of occupancy levels, further comprising:

determining a maximum occupancy level from the plurality of occupancy levels by the channel-bonding control circuit;

computing a plurality of occupancy differences from differences between the maximum occupancy level and each of the plurality of occupancy levels; and

computing a plurality of bit slip numbers from the plurality of occupancy differences; and

reducing a bit slip number by a width of a parallel data signal when the bit slip number is greater than the width of the parallel data signal.

18. A circuit for low-skew bonding of a plurality of data channels into a multi-lane data channel, the circuit comprising:

a plurality of phase-measuring first-in first-out buffer circuits which buffer a plurality of parallel data signals and generate a plurality of phase-measurement signals which measure phases of the plurality of parallel data signals;

a channel-bonding control circuit which receives the plurality of phase-measurement signals from the plurality of phase-measuring first-in first-out buffer circuits and outputs a plurality of clock-slip control signals; and

a plurality of clock slip circuits that generate a plurality of slipped clock signals by controllably slipping a plurality of parallel clock signals by integer numbers of unit intervals of a serial clock signal, wherein the integer numbers of unit intervals are determined from the plurality of clock-slip control signals.

19. A method of low-skew bonding of a plurality of data channels into a multi-lane data channel, the method comprising:

buffering a plurality of parallel data signals by a plurality of phase-measuring first-in first-out buffer circuits;

outputting a plurality of phase-measurement signals by the plurality of phase-measuring first-in first-out buffer circuits, wherein the plurality of phase-measurement signals measure phases of the plurality of parallel data signals;

receiving the plurality of phase-measurement signals by a channel-bonding control circuit from the plurality of phase-measuring first-in first-out buffer circuits;

outputting a plurality of clock-slip control signals by the channel-bonding control circuit; and

generating a plurality of slipped clock signals by controllably slipping a plurality of parallel clock signals by integer numbers of unit intervals of a serial clock signal, wherein the integer numbers of unit intervals are determined from the plurality of clock-slip control signals.