Efficient controllers and implementations for elastic buffers
View Patent ↗Systems and methods relating to an elastic buffer for dynamically adjusting depth of a data-path implemented on an integrated circuit device. The device includes a first flip-flop, a second flip-flop, a multiplexer, and a controller. The first and second flip-flops are arranged in a cascade configuration with the multiplexer interposed therebetween. In certain embodiments, the multiplexer is capable of selecting between input received upstream and the output of the first flip-flop. The controller utilizes control logic to drive the first and second flip-flops and the multiplexer. The first and second flip-flops, and the multiplexer may represent an elastic buffer subunit corresponding to a single bit within a larger elastic buffer, in which a plurality of elastic buffer subunits are cascaded to form the elastic buffer along with a single shared controller.
1. An elastic buffer for dynamically adjusting a depth of a data-path implemented on an integrated circuit device, the elastic buffer comprising:
a first flip-flop;
a second flip-flop;
a multiplexer, wherein the first flip-flop and the second flip-flop are arranged in a cascade configuration with the multiplexer interposed therebetween; and
a controller that utilizes control logic to:
drive the first flip-flop and the second flip-flop and the multiplexer, and
generate enable signals as inputs for each of the first flip-flop and the second flip-flop and a select signal as an input for the multiplexer.
2. The elastic buffer of claim 1 , wherein each of the first flip-flop, the second flip-flop, and the multiplexer correspond to a single bit in the elastic buffer.
3. The elastic buffer of claim 1 , wherein the controller comprises:
a first state register and a second state register arranged in a parallel configuration; and
a first 2-input gate and a second 2-input gate for driving the first state register and the second state registers, respectively.
4. The elastic buffer of claim 3 , wherein the controller utilizes next state logic based on the first state register and the second state register.
5. The elastic buffer of claim 4 , wherein the next state logic is one gate deep.
6. The elastic buffer of claim 1 , wherein the control logic generates clock gating signals.
7. The elastic buffer of claim 1 , wherein the multiplexer is selectable by the controller to dynamically change a depth of the elastic buffer between one position deep and two positions deep.
8. A logic module for implementing a flip-flop-based elastic buffer on an integrated circuit device, the logic module comprising:
a first flip-flop;
a second flip-flop arranged in a cascade configuration with the first flip-flop; and
a multiplexer, wherein:
inputs to each of the first flip-flop and the second flip-flop are driven by the multiplexer, and
a select input of the multiplexer is driven at least in part by user-configurable logic.
9. The logic module of claim 8 , wherein the select input of the multiplexer is further driven by a plurality of configuration bits.
10. The logic module of claim 8 further comprising a controller for driving the multiplexer.
11. The logic module of claim 10 , wherein the controller comprises:
a first state register and a second state register arranged in a parallel configuration; and
a first 2-input gate and a second 2-input gate for driving the first state register and the second state registers, respectively.
12. The logic module of claim 11 , wherein the controller is configured to generate clock gating signals based on control logic.
13. The logic module of claim 10 , wherein the multiplexer is selectable by the controller to dynamically change a depth of the flip-flop-based elastic buffer between one position deep and two positions deep.
14. A non-transient, machine-readable medium for mapping elastic buffers of a user design in a logic module of an integrated circuit, wherein the non-transient machine-readable medium for mapping the elastic buffers of the user design in the logic module of the integrated circuit contains instructions encoded thereon for:
identifying an elastic buffer in the user design;
identifying a flip-flop pair within the logic module;
automatically mapping the elastic buffer to the flip-flop pair such that an elastic buffer controller drives a multiplexer interposed with the flip-flop pair; and
mapping user-configurable logic to the elastic buffer such that the multiplexer is driven at least in part by the user-configurable logic.
15. The non-transient, machine-readable medium of claim 14 further including instructions encoded thereon for automatically converting at least one internal control signal of the elastic buffer into a clock gating signal using clock gating resources of the programmable logic device.
16. The non-transient, machine-readable medium of claim 15 , wherein the buffer controller utilizes control logic to drive the flip-flop pair and the multiplexer.
17. The non-transient, machine-readable medium of claim 16 , wherein the buffer controller further utilizes the control logic to generate clock gating signals.
18. The non-transient, machine-readable medium of claim 14 further including instructions encoded thereon for utilizing control logic to dynamically change a depth of the mapped elastic buffer between one position deep and two positions deep.
19. An elastic buffer for dynamically adjusting a depth of a data-path implemented on an integrated circuit device, the elastic buffer comprising:
a first flip-flop;
a second flip-flop;
a multiplexer, wherein the first flip-flop and the second flip-flop are arranged in a cascade configuration with the multiplexer interposed therebetween; and
a controller that utilizes control logic to drive the first flip-flop and the second flip-flop and the multiplexer, wherein the controller comprises a first state register and a second state register arranged in a parallel configuration.
20. An elastic buffer for dynamically adjusting a depth of a data-path implemented on an integrated circuit device, the elastic buffer comprising:
a first flip-flop;
a second flip-flop;
a multiplexer, wherein the first flip-flop and the second flip-flop are arranged in a cascade configuration with the multiplexer interposed therebetween; and
a controller that utilizes control logic to drive the first flip-flop and the second flip-flop and the multiplexer, wherein the multiplexer is selectable by the controller to dynamically change a depth of the elastic buffer between one position deep and two positions deep.
21. A non-transient, machine-readable medium for mapping elastic buffers of a user design in a logic module of an integrated circuit, wherein the non-transient machine-readable medium for mapping the elastic buffers of the user design in the logic module of the integrated circuit contains instructions encoded thereon for:
identifying an elastic buffer in the user design;
identifying a flip-flop pair within the logic module;
automatically mapping the elastic buffer to the flip-flop pair such that an elastic buffer controller drives a multiplexer interposed with the flip-flop pair; and
automatically converting at least one internal control signal of the elastic buffer into a clock gating signal using clock gating resources of the programmable logic device.
22. A non-transient, machine-readable medium for mapping elastic buffers of a user design in a logic module of an integrated circuit, wherein the non-transient machine-readable medium for mapping the elastic buffers of the user design in the logic module of the integrated circuit contains instructions encoded thereon for:
identifying an elastic buffer in the user design;
identifying a flip-flop pair within the logic module;
automatically mapping the elastic buffer to the flip-flop pair such that an elastic buffer controller drives a multiplexer interposed with the flip-flop pair; and
utilizing control logic to dynamically change a depth of the mapped elastic buffer between one position deep and two positions deep.