Equalization circuitry including a digital-to-analog converter having a voltage divider and a multiplexer

1. An equalization circuitry comprising:

a digital-to-analog converter including:

a voltage divider; and

a multiplexer coupled to the voltage divider;

a state machine counter coupled to the digital-to-analog converter, wherein the state machine counter provides a selection signal to the multiplexer;

a plurality of equalizer control logic circuits coupled to the digital-to-analog converter; and

a control logic circuit selection logic to provide a selection signal for selecting an equalizer control logic circuit from the plurality of equalizer control logic circuits.

2. The equalization circuitry of claim 1 , wherein the plurality of equalizer control logic circuits includes a plurality of single-stage equalizer control logic circuits and wherein the digital-to-analog converter provides a control signal to the plurality of single-stage equalizer control logic circuits.

3. The equalization circuitry of claim 1 , wherein the multiplexer receives a plurality of inputs from the voltage divider and selects an output from the plurality of inputs.

4. The equalization circuitry of claim 1 , wherein the voltage divider includes a plurality of resistors coupled in series.

5. The equalization circuitry of claim 4 , wherein the voltage divider further includes a first resistor coupled to the plurality of resistors, ground, and a lowest voltage input terminal of the multiplexer, further wherein a voltage across the first resistor is an input voltage to the lowest voltage input terminal.

6. The equalization circuitry of claim 5 , wherein the first resistor includes a second plurality of resistors coupled in series and a plurality of transistors, wherein each transistor of the plurality of transistors is coupled to ground and a corresponding resistor of the second plurality of resistors.

7. The equalization circuitry of claim 5 , wherein the voltage divider further includes a second resistor coupled to the plurality of resistors and a supply voltage, further wherein the supply voltage minus a voltage across the second resistor and a voltage across a resistor of the plurality of resistors is an input voltage to a highest voltage input terminal of the multiplexer.

8. The equalization circuitry of claim 7 , wherein the first and second resistors are programmable in user mode.

9. The equalization circuitry of claim 1 further comprising:

an equalizer including a plurality of equalization stages;

wherein the plurality of equalizer control logic circuits includes:

a multi-stage equalizer control logic circuit coupled to the equalizer; and

a plurality of single-stage equalizer control logic circuits coupled to the digital-to-analog converter and the equalizer, wherein each single-stage equalizer control logic circuit of the plurality of single-stage equalizer control logic circuits is coupled to a corresponding equalization stage of the plurality of equalization stages.

10. The equalization circuitry of claim 9 , wherein

the control logic circuit selection logic is coupled to the digital-to-analog converter, the multi-stage equalizer control logic circuit, and the plurality of single-stage equalizer control logic circuits, wherein the state machine counter is coupled to the multi-stage equalizer control logic circuit and the plurality of single-stage equalizer control logic circuits and the control logic circuit selection logic provides the selection signal for selecting an equalizer control logic circuit from the multi-stage equalizer control logic circuit and the plurality of single-stage equalizer control logic circuits.

11. The equalization circuitry of claim 10 further comprising:

a reference edge generator coupled to the equalizer;

a first high pass filter coupled to the equalizer and an input terminal of the reference edge generator;

a second high pass filter coupled to an output terminal of the reference edge generator;

a first rectifier coupled to an output terminal of the first high pass filter;

a second rectifier coupled to an output terminal of the second high pass filter; and

a comparator coupled to an output terminal of the first rectifier, an output terminal of the second rectifier, and an up/down input terminal of the state machine counter.

12. A programmable logic device including the equalization circuitry of claim 1 .

13. A digital system comprising a programmable logic device including the equalization circuitry of claim 1 .

14. A method of equalization, the method comprising:

voltage dividing a voltage signal into a plurality of voltage signals;

selecting one voltage signal from the plurality of voltage signals;

controlling an equalizer with the one voltage signal;

using a state machine counter to provide a selection signal for the selecting the one voltage signal; and

using a control logic circuit selection logic to provide a selection signal for selecting an equalizer control logic circuit from a plurality of equalizer control logic circuits.

15. The method of claim 14 , wherein the voltage dividing includes applying the voltage signal to a plurality of resistors coupled in series.

16. The method of claim 14 , wherein the voltage dividing includes applying the voltage signal to a plurality of resistors coupled in series, wherein the plurality of resistors includes a first plurality of resistors coupled in series and a programmable resistor coupled to ground and the first plurality of resistors, further wherein a lowest voltage of the plurality of voltage signals is a non-zero voltage signal.

17. The method of claim 14 , wherein the voltage dividing includes applying the voltage signal to a plurality of resistors coupled in series, wherein the plurality of resistors includes a first plurality of resistors coupled in series, a first programmable resistor coupled to ground and the first plurality of resistors, and a second programmable resistor coupled to the voltage signal and the first plurality of resistors, further wherein a lowest voltage of the plurality of voltage signals is a non-zero voltage signal and a highest voltage of the plurality of voltage signals is the voltage signal minus a voltage across a resistor of the first plurality of resistors and a voltage across the second programmable resistor.

18. The method of claim 14 further comprising:

providing an equalizer output to a reference edge generator;

first high pass filtering the equalizer output;

second high pass filtering an output of the reference edge generator;

first rectifying an output of the first high pass filtering;

second rectifying an output terminal of the second high pass filtering;

comparing an output of the first rectifying and an output of the second rectifying; and

providing an output of the comparing to increment or decrement a count of the state machine counter.

19. The method of claim 14 , wherein the plurality of equalizer control logic circuits comprise a multi-stage equalizer control logic circuit and a plurality of single-stage equalizer control logic circuits, wherein each single-stage equalizer control logic circuit of the plurality of single-stage equalizer control logic circuits is coupled to a corresponding equalization stage of a plurality of equalization stages of the equalizer.

20. An equalization circuitry comprising:

(a) a digital-to-analog converter including:

(i) a voltage divider including a first plurality of resistors coupled in series and a first programmable resistor coupled to the first plurality of resistors and ground; and

(ii) a multiplexer coupled to the voltage divider, wherein the multiplexer receives a plurality of inputs from the voltage divider and selects an output from the plurality of inputs, further wherein the first programmable resistor is coupled to a lowest voltage input terminal of the multiplexer, and a voltage across the first programmable resistor is an input voltage to the lowest voltage input terminal;

(b) an equalizer including a plurality of equalization stages;

(c) a multi-stage equalizer control logic circuit coupled to the digital-to-analog converter and the equalizer, wherein the multi-stage equalizer control logic circuit is coupled to the plurality of equalization stages;

(d) a plurality of single-stage equalizer control logic circuits coupled to the digital-to-analog converter and the equalizer, wherein the digital-to-analog converter provides a control signal to the multi-stage equalizer control logic circuit and the plurality of single-stage equalizer control logic circuits, further wherein each single-stage equalizer control logic circuit of the plurality of single-stage equalizer control logic circuits is coupled to a corresponding equalization stage of the plurality of equalization stages; and

(e) a state machine counter and a control logic circuit selection logic coupled to the digital-to-analog converter, the multi-stage equalizer control logic circuit, and the plurality of single-stage equalizer control logic circuits, wherein the state machine counter provides a selection signal to the multiplexer and the control logic circuit selection logic provides a selection signal for selecting an equalizer control logic circuit from the multi-stage equalizer control logic circuit and the plurality of single-stage equalizer control logic circuits.

21. The equalization circuitry of claim 20 , wherein the first programmable resistor includes a second plurality of resistors coupled in series and a plurality of transistors, wherein each transistor of the plurality of transistors is coupled to ground and a corresponding resistors of the second plurality of resistors, further wherein the voltage divider further includes a second programmable resistor coupled to the first plurality of resistors and a supply voltage, further wherein the supply voltage minus a voltage across the second programmable resistor and a voltage across a resistor of the first plurality of resistors is an input voltage to a highest voltage input terminal of the multiplexer.

22. The equalization circuitry of claim 20 further comprising:

a reference edge generator coupled to the equalizer;

a first high pass filter coupled to the equalizer and an input terminal of the reference edge generator;

a second high pass filter coupled to an output terminal of the reference edge generator;

a first rectifier coupled to an output terminal of the first high pass filter;

a second rectifier coupled to an output terminal of the second high pass filter; and

a comparator coupled to an output terminal of the first rectifier, an output terminal of the second rectifier, and an up/down input terminal of the state machine counter.

23. A programmable logic device including the equalization circuitry of claim 20 .

24. A digital system comprising a programmable logic device including the equalization circuitry of claim 20 .