Distributed multi-die protocol application interface
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.
1. A single package multi-die electronic device comprising:
a communication bus comprising a plurality of channels;
a first die comprising a first bus interface coupled to the communication bus; and
a second die comprising:
a second bus interface coupled to the communication bus; and
data processing circuitry configurable to exchange data with the first die over the communication bus, wherein the plurality of channels comprises:
a first set of unidirectional channels extending from the first bus interface to the second bus interface; or
a second set of unidirectional channels extending from the second bus interface to the first bus interface.
2. The single package multi-die electronic device of claim 1 , wherein the first bus interface is configurable to transmit source synchronous data to the second bus interface using the communication bus.
3. The single package multi-die electronic device of claim 2 , wherein the second die comprises circuitry to synchronize a plurality of data signals of the source synchronous data.
4. The single package multi-die electronic device of claim 3 , wherein the communication bus comprises a clock signal line.
5. The single package multi-die electronic device of claim 4 , wherein the circuitry of the second die is configurable to synchronize the plurality of data signals of the source synchronous data by latching the received source synchronous data using a clock signal transmitted from the first bus interface over the clock signal line.
6. The single package multi-die electronic device of claim 2 , wherein the source synchronous data comprises peripheral component express (PCIe) data, memory data, or both.
7. The single package multi-die electronic device of claim 1 , wherein the plurality of channels comprises the first set of unidirectional channels.
8. The single package multi-die electronic device of claim 1 , wherein the plurality of channels comprises the second set of unidirectional channels.
9. The single package multi-die electronic device of claim 1 , wherein the plurality of channels comprises the first set of unidirectional channels and the second set of unidirectional channels.
10. The single package multi-die electronic device of claim 1 , wherein the second die comprises a processor or a programmable logic device.
11. The single package multi-die electronic device of claim 1 , wherein the first die comprises a third bus interface to couple the second die to a memory device.
12. A system comprising:
a memory device;
a communication bus comprising a plurality of channels;
an input/output (I/O) die comprising a first bus interface coupled to the communication bus; and
an integrated circuit die comprising:
a second bus interface coupled to the communication bus; and
data processing circuitry configurable to exchange data with the IO die over the communication bus, wherein the plurality of channels comprises:
a first set of unidirectional channels extending from the first bus interface to the second bus interface; or
a second set of unidirectional channels extending from the second bus interface to the first bus interface.
13. The system of claim 12 , wherein the first bus interface is configurable to provide source synchronous data to the second bus interface using the communication bus.
14. The system of claim 12 , wherein:
the communication bus comprises a clock signal line; and
the IO die comprises an on-die interconnect to couple the first bus interface to the second bus interface.
15. The system of claim 14 , wherein a clock frequency associated with the second bus interface and a clock frequency associated with the on-die interconnect are separately settable.
16. The system of claim 15 , wherein:
in a first configuration, the clock frequency associated with the second bus interface is different from the clock frequency associated with the on-die interconnect; and
in a second configuration, the clock frequency associated with the on-die interconnect and the clock frequency associated with the second bus interface are the same.
17. An electronic device comprising:
a communication bus comprising a plurality of channels;
an input/output (I/O) die comprising a first bus interface coupled to the communication bus; and
an integrated circuit die comprising:
a second bus interface coupled to the communication bus; and
data processing circuitry configurable to exchange data with the IO die over the communication bus, wherein the plurality of channels comprises:
a first set of unidirectional channels extending from the first bus interface to the second bus interface; or
a second set of unidirectional channels extending from the second bus interface to the first bus interface.
18. The electronic device of claim 17 , wherein the integrated circuit die comprises programmable logic.
19. The electronic device of claim 17 , wherein the integrated circuit die comprises a processor.
20. The electronic device of claim 17 , wherein:
the communication bus comprises a clock signal line;
the IO die comprises an on-die interconnect to couple the first bus interface to the second bus interface;
a clock frequency associated with the second bus interface and a clock frequency associated with the on-die interconnect are separately settable;
in a first configuration, the clock frequency associated with the second bus interface is different from the clock frequency associated with the on-die interconnect; and
in a second configuration, the clock frequency associated with the on-die interconnect and the clock frequency associated with the second bus interface are the same.