Methods and apparatus for selectively extracting and loading register states
Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
1. A server, comprising:
registers, a first portion of which is configured to store a first type of register states and a second portion of which is configured to store a second type of register states that is different than the first type of register states, wherein the first type of register states comprises one or more non-critical states, and wherein the second type of register states comprises one or more critical states; and
means for migrating the second type of register states from the server to a destination server, wherein migrating the second type of register states comprises uniquely identifying the second type of register states to track criticality for operation.
2. The server of claim 1 , wherein the means for migrating the second type of register states comprise extraction circuitry configured to extract the second type of register states from the registers without extracting the first type of register states.
3. The server of claim 2 , wherein the extraction circuitry comprises a multiplexing circuit, a scan chain, a debug circuit, or a finite state machine.
4. The server of claim 1 , wherein the registers are part of a programmable device.
5. A system, comprising:
a first server including a first set of registers configured to store a first type of register states and a second set of registers configured to store a second type of register states different than the first type of register states, wherein the first type of register states comprises one or more non-critical states; and
a second server configured to receive the second type of register states from the first server, wherein the second type of register states comprises one or more critical states uniquely identified as critical for operation and receiving the second type of register states is based at least in part on the tracked criticality using the unique identifiers.
6. The system of claim 5 , wherein the first server comprises extraction circuitry configured to extract the second type of register states from the second set of registers without extracting the first type of register states from the first set of registers.
7. The system of claim 6 , wherein the extraction circuitry comprises a multiplexing circuit.
8. The system of claim 6 , wherein the extraction circuitry comprises a scan chain.
9. The system of claim 6 , wherein the extraction circuitry comprises a debug circuit.
10. The system of claim 6 , wherein the extraction circuitry comprises a finite state machine.
11. The system of claim 5 , wherein the first server comprises a host processor and a separate programmable processor coupled to the host processor.
12. The system of claim 5 , wherein the second server comprises a host processor and a separate programmable processor coupled to the host processor.
13. A method, comprising:
storing a first type of register states in a first set of registers of a first server, wherein the first type of register states comprises one or more non-critical states;
storing a second type of register states in a second set of registers of the first server wherein the second type of register states comprises one or more critical states;
uniquely identifying the second type of register states to indicate criticality of the second type of register states for operation; and
migrating, based at least in part on the unique identification, the second type of register states from the first server to a second server without migrating the first type of register states.
14. The method of claim 13 , wherein migrating the second type of register states from the first server to the second server comprises extracting the second type of register states from the registers without extracting the first type of register states.
15. The method of claim 13 , wherein the first server is configured to run a first application and the method comprises, after migrating the second type of register states from the first server to the second server, reconfiguring the first server to run a second application.
16. The method of claim 13 , wherein the second type of register states are migrated from the first server to the second server after all pending transactions on the first server have completed.
17. The method of claim 13 , wherein migrating the second type of register states from the first server to the second server comprises writing the second type of register states to a third set of registers of the second server.