Patent Assignment
Reel/Frame 072324/0430
Assignment of Assignor's Interest
Recorded: 2025-09-22
Pages: 9
Assignor
INTEL CORPORATION
Executed: 2025-09-11
Assignee
ALTERA CORPORATION
101 INNOVATION DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(30)
Methods and Apparatus for Programmable Integrated Circuit Coprocessor Sector Management
Application:
15/358,665 →
Publication:
US US20180143860A1
Embedded Multi-Die Interconnect Bridge with Improved Power Delivery
Application:
15/439,118 →
Publication:
US US20180240778A1
Efficient and Scalable Network-on-Chip Topology for High-Bandwidth Memory, and Applications
Application:
62/722,741 →
First-In First-Out Buffer with Lookahead Performance Booster
Application:
63/081,134 →
Lower Precision Neural Network Systems and Methods
Application:
62/488,636 →
Embedded Network on Chip Accessible to Programmable Logic Fabric of Programmable Logic Device in Multi-Dimensional Die Systems
Application:
18/797,325 →
Publication:
US US20240396555A1
Floating-Point Dynamic Range Expansion
Application:
18/754,921 →
Publication:
US US20240345804A1
Scalable Network-on-Chip for High-Bandwidth Memory
Floating-Point Decomposition Circuitry with Dynamic Precision
Floating-Point Decomposition Circuitry with Dynamic Precision
Application:
19/002,480 →
Publication:
US US20250123801A1
Stacked Die Network Interface Controller Circuitry
Application:
18/757,034 →
Publication:
US US20240347514A1
Logic Fabric Based on Microsector Infrastructure
Application:
18/795,146 →
Publication:
US US20240396556A1
Logic Fabric Based on Microsector Infrastructure with Data Register Having Scan Registers
Application:
18/621,940 →
Publication:
US US20240241650A1
Programmable Integrated Circuit Underlay
Application:
18/796,279 →
Publication:
US US20240394448A1
Circuit Design Visibility in Integrated Circuit Devices
First-In First-Out Buffer with Lookahead Performance Booster
Application:
18/912,326 →
Publication:
US US20250036157A1
Micro-Network-On-Chip and Microsector Infrastructure
Application:
18/912,321 →
Publication:
US US20250036591A1
Distributed Attestation in Heterogenous Computing Clusters
Application:
19/299,604 →
Publication:
US US20250373449A1
Integrated Circuit Package with Electro-Optical Interconnect Circuitry
Application:
18/795,148 →
Publication:
US US20240418951A1
Programmable Logic Device Virtualization
Methods And Apparatus For Selectively Extracting And Loading Register States
Short Link Efficient Interconnect Circuitry
Short Link Efficient Interconnect Circuitry
Short Link Efficient Interconnect Circuitry
Scalable Network-on-Chip for High-Bandwidth Memory
Scalable Network-on-Chip for High-Bandwidth Memory
Via-Configurable High-Performance Logic Block Architecture
Method, Device and System for Multi Field Classification in a Data Communications Network
Integrated Circuit Package with Electro-Optical Interconnect Circuitry
Integrated Circuit Package with Electro-Optical Interconnect Circuitry
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 22, 2016
From: DASU, ARAVIND; WEBER, SCOTT; TAN, JUN PIN; RAHMAN, ARIFUR
To: INTEL CORPORATION
Reel/Frame 040401/0804 →
Assignment of Assignor's Interest
Feb 22, 2017
From: LIU, HUI; OH, KYUNG SUK
To: INTEL CORPORATION
Reel/Frame 041339/0032 →
Assignment of Assignor's Interest
Feb 15, 2019
From: TEH, CHEE HAK; ONG, YU YING; OOI, GEORGE CHONG HEAN
To: INTEL CORPORATION
Reel/Frame 048346/0287 →
Assignment of Assignor's Interest
Feb 19, 2019
From: WU, HSINHO; SHIMANOUCHI, MASASHI; LI, PENG
To: INTEL CORPORATION
Reel/Frame 048372/0688 →
Assignment of Assignor's Interest
Oct 26, 2020
From: FOO, KOK YOONG; LEE, SZE YIN
To: INTEL CORPORATION
Reel/Frame 054213/0425 →
Assignment of Assignor's Interest
Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
Security Interest
Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →