Floating-point decomposition circuitry with dynamic precision
Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.
1. An integrated circuit, comprising:
first circuitry configurable to:
receive a first floating point number and a second floating point number; and
dynamically choose a precision to convert the first floating point number and the second floating point number into a plurality of components, wherein the plurality of components has a precision less than a precision of at least one of the first floating point number or of the second floating point number; and
second circuitry configurable to perform multiplication operations using the plurality of components.
2. The integrated circuit of claim 1 , wherein the second circuitry comprises an accumulator.
3. The integrated circuit of claim 2 , wherein the accumulator is configurable to generate an output by accumulating the plurality of components, the output having the precision greater than or equal to the precision of the first floating point number or the second floating point number.
4. The integrated circuit of claim 1 , wherein the first circuitry comprises circuitry to dynamically select the precision of the plurality of components.
5. The integrated circuit of claim 1 , wherein the plurality of components comprises a 2-bit mantissa or a 3-bit mantissa.
6. The integrated circuit of claim 1 , wherein the integrated circuit is a graphics processing unit (GPU).
7. The integrated circuit of claim 1 , comprising a memory configurable to store a plurality of floating point numbers in a first precision or a second precision.
8. The integrated circuit of claim 1 , comprising input/output circuitry configurable for off-die communication.
9. The integrated circuit of claim 1 , wherein the second circuitry is configurable to multiply a first component of the plurality of components and a second component of the plurality of components in parallel with a third component of the plurality of components and a fourth component of the plurality of components.
10. A method, comprising:
receiving, via processing circuitry, a first floating point number and a second floating point number from memory;
dynamically choosing, via the processing circuitry, a precision to convert the first floating point number and the second floating point number into a plurality of components, wherein the plurality of components has a precision less than a precision of a least one of the first floating point number or of the second floating point number; and
performing, via matrix multiply-accumulate circuitry, multiplication operations using the plurality of components.
11. The method of claim 10 , wherein performing, via the matrix multiply-accumulate circuitry, the plurality of components comprises:
multiplying a first component of the plurality of components and a second component of the plurality of components; and
multiplying a third component of the plurality of components and a fourth component of the plurality of components at the same time.
12. The method of claim 10 , wherein performing, via the matrix multiply-accumulate circuitry, the plurality of components comprises:
accumulating a first component of the plurality of components and a second component of the plurality of components; and
accumulating a third component of the plurality of components and a fourth component of the plurality of components in parallel.
13. The method of claim 10 , wherein dynamically choosing, via the processing circuitry, the precision to convert the first floating point number and the second floating point number comprises:
generating a select signal indicative of the precision of the plurality of components.
14. The method of claim 13 , wherein the precision of the plurality of components comprises a 2-bit mantissa or a 3-bit mantissa.
15. A data processing system, comprising:
a memory configurable to store a plurality of floating point numbers;
an integrated circuit configurable to support an operation, the integrated circuit comprising:
first circuitry configurable to:
receive a first floating point number of the plurality of floating point numbers and a second floating point number of the plurality of floating point numbers; and
dynamically choosing a precision to convert the first floating point number and the second floating point number into a plurality of components, wherein the plurality of components has a precision less than a precision of at least one of the first floating point number or the second floating point number; and
second circuitry configurable to perform multiplication operations using the plurality of components.
16. The data processing system of claim 15 , wherein the second circuitry is an accumulator configurable to generate an output by accumulating the plurality of components, the output having the precision greater than or equal to the precision of the first floating point number or the second floating point number.
17. The data processing system of claim 15 , wherein the first circuitry comprises circuitry configurable to comprises circuitry to dynamically select the precision of the plurality of components.
18. The data processing system of claim 15 , wherein the second circuitry is configurable to perform the multiplication operations using a first component of the plurality of components and a second component of the plurality of components in parallel with a third component of the plurality of components and a fourth component of the plurality of components.
19. The data processing system of claim 15 , wherein the plurality of components comprises a 2-bit mantissa or a 3-bit mantissa.
20. The data processing system of claim 15 , wherein the integrated circuit is a graphics processing unit (GPU).