Method and apparatus for performing fast incremental resynthesis
View Patent ↗A method for designing a system on a target device is disclosed. Extraction is performed on a first version of the system during synthesis in a first compilation resulting in a first netlist. Optimizations are performed on the first version of the system during synthesis in the first compilation resulting in a second netlist. Placement and routing are performed on the first version of the system in the first compilation. Extraction is performed on a second version of the system having a changed portion during synthesis in a second compilation resulting in a third netlist. The first version of the system in the first netlist and the second version of the system in the third netlist are differentiated to identify identical regions, wherein at least one of the performing and differentiating is performed by a processor.
1. A method for designing a system on a target device,
performing extraction on a first version of the system during synthesis in a first compilation resulting in a first netlist;
performing optimizations on the first version of the system during synthesis in the first compilation resulting in a second netlist;
performing placement and routing on the first version of the system in the first compilation;
performing extraction on a second version of the system having a changed portion during synthesis in a second compilation resulting in a third netlist; and
differentiating the first version of the system in the first netlist and the second version of the system in the third netlist to identify identical regions, wherein at least one of the performing and differentiating is performed by a processor.
2. The method of claim 1 , further comprising replacing an identical region on the third netlist with an optimized version of the identical region from the second netlist.
3. The method of claim 1 , further comprising performing optimizations on the changed portion of the second version of the system during synthesis lathe second compilation without performing optimizations on the identical regions.
4. The method of claim 1 , further comprising performing optimizations on the changed portion of the second version of the system during synthesis in the second compilation by using timing information from placement and routing of the first version of the system.
5. The method of claim 4 , wherein using the timing information comprises deriving an upper bound on an amount of logic delay that can be added on a path.
6. The method of claim 1 , wherein performing optimizations on the first version of the system during synthesis in the first compilation resulting in a second netlist comprises performing register duplication, register merging, and register retiming.
7. The method of claim 1 , wherein differentiating the first version of the system in the first netlist and the second version of the system in the third netlist comprises performing a functional differentiation procedure.
8. The method of claim 1 , wherein performing extraction during synthesis comprises creating a structural representation of a system from a high level description.
9. The method of claim 1 , wherein performing optimizations during synthesis comprises performing procedures to reduce area and improve speed and performing mapping to create a netlist of logic blocks supported by the target device.
10. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising:
performing extraction on a first version of a system during synthesis in a first compilation resulting in a first netlist;
performing optimizations on the first version of the system during synthesis in the first compilation resulting in a second netlist;
performing placement and routing on the first version of the system in the first compilation;
performing extraction on a second version of the system having a changed portion during synthesis in a second compilation resulting in a third netlist; and
differentiating the first version of the system in the first netlist and the second version of the system in the third netlist to identify identical regions.
11. The non-transitory computer readable medium of claim 10 , wherein the method further comprises replacing an identical region on the third netlist with an optimized version of the identical region from the second netlist.
12. The non-transitory computer readable medium of claim 10 , wherein the method further comprises performing optimizations on the changed portion of the second version of the system during synthesis in the second compilation without performing optimizations on the identical regions.
13. The non-transitory computer readable medium of claim 10 , wherein the method further comprises performing optimizations on the changed portion of the second version of the system during synthesis in the second compilation by using timing information from placement and routing of the first version of the system.
14. The non-transitory computer readable medium of claim 13 , wherein using the timing information comprises deriving an upper bound on an amount of logic delay that can be added on a path.
15. The non-transitory computer readable medium of claim 10 , wherein performing optimizations on the first version of the system during synthesis in the first compilation resulting in a second netlist comprises performing register duplication, register merging, and register retiming.
16. The non-transitory computer readable medium of claim 10 , wherein differentiating the first version of the system in the first netlist and the second version of the system in the third netlist comprises performing a functional differentiation procedure.
17. The non-transitory computer readable medium of claim 10 , wherein performing extraction during synthesis comprises creating a structural representation of a system from a high level description.
18. The non-transitory computer readable medium of claim 10 , wherein performing optimizations during synthesis comprises performing procedures to reduce area and improve speed and performing mapping to create a netlist of logic blocks supported by the target device.
19. A system designer, comprising:
a synthesis unit to perform extraction of a first version of a system resulting in a first netlist, optimization on the first version of the system resulting in a second netlist, and extraction of a second version of the system having a changed portion resulting in a third netlist;
a differentiation unit to differentiate the first version of the system in the first netlist and the second version of the system in the third netlist to identify identical regions.
20. The system designer of claim 19 , wherein the synthesis unit further comprising a replacement unit to replace an identical region on the third netlist with an optimized version of the identical region from the second netlist.
21. The system designer of claim 19 , wherein the synthesis unit performs optimizations on the changed portion of the second version of the system during synthesis in the second compilation without performing optimizations on the identical regions.
22. The system designer of claim 19 , further comprising:
a placement unit to place the first version of the system on the target device; and
a muter to route the first version of the system on the target device.
23. The method of claim 19 , wherein the synthesis unit performs optimizations on the changed portion of the second version of the system during synthesis in the second compilation by using timing information from placement and muting of the first version of the system.