Methods and apparatus for providing redundancy on multi-chip devices

1. A method comprising:

partitioning first and second integrated circuit dies into a plurality of logic regions, the first and second integrated circuit dies each including a spare logic region, wherein corresponding logic regions of the first and second integrated circuit dies are coupled using interconnects on a multi-chip package that includes the first and second integrated circuit dies;

forming a plurality of logic groups, each logic group comprising a configurable logic region on the first integrated circuit die that performs a first user logic function and a corresponding configurable logic region on the second integrated circuit die that performs a second user logic function, wherein the logic regions of the logic group are coupled using the interconnects on the multi-chip package;

evaluating the plurality of logic groups to identify a defective logic group; and

in response to identifying the defective logic group, repairing the defective logic group by configuring the first and second integrated circuit dies to stop using the defective logic group and use a spare logic group comprising the spare logic regions of the first and second integrated circuit dies, wherein the spare logic regions are coupled using spare logic region interconnects on the multi-chip package.

2. The method defined in claim 1 wherein repairing the defective logic group comprises:

substituting the logic regions of the defective logic group with the spare logic regions of the spare logic group.

3. The method defined in claim 1 wherein identifying the defective logic group comprises determining whether any one of the logic regions or interconnects of the defective logic group is defective.

4. The method defined in claim 1 wherein the logic groups are organized in an order, wherein repairing the defective logic group comprises:

substituting each successive logic group in the order following the defective logic group with a previous logic group.

5. The method defined in claim 1 wherein the spare logic regions of the first and second integrated circuit dies are coupled by the spare logic region interconnects, the method further comprising:

in response to identifying the defective logic group, configuring the multi-chip package to use the spare logic region interconnects instead of the interconnect from the defective logic group.

6. The method defined in claim 5 wherein the first and second integrated circuit die are mounted on an interposer, wherein the interconnect and the additional interconnect are formed at least partly in the interposer, and wherein configuring the integrated circuit package to use the spare logic regions of the first and second integrated circuit dies comprises:

configuring the spare logic region of the first integrated circuit die to perform the first logic function; and

configuring the spare logic region of the second integrated circuit die to perform the second logic function.

7. The method defined in claim 5 wherein the first integrated circuit die is mounted on the second integrated circuit die, wherein the interconnect and the additional interconnect include through-silicon vias in the first integrated circuit die, and wherein configuring the integrated circuit package to use the spare logic regions of the first and second integrated circuit dies comprises:

configuring the spare logic region of the first integrated circuit die to communicate with the spare logic region of the second integrated circuit die via the additional interconnect; and

configuring another spare logic region from the second integrated circuit die to communicate with a spare logic region from a third integrated circuit die via another additional interconnect.

8. A method of manufacturing an integrated circuit package, the method comprising:

forming a plurality of logic groups from first and second logic circuitries, the first and second logic circuitries each including a plurality of logic regions and at least one spare logic region, wherein corresponding logic regions of the first and second logic circuitries are coupled using interconnects on the integrated circuit package that includes the first and second logic circuitries;

evaluating the plurality of logic groups to identify a defective logic group by determining whether any one of the logic regions of the defective logic group is defective; and

in response to identifying the defective logic group, repairing the defective logic group by configuring the integrated circuit package to use a spare logic group instead of the defective logic group, wherein the spare logic group comprising spare logic regions of the first and second logic circuitries.

9. The method defined in claim 8 , further comprising:

identifying defective logic region from the plurality of logic regions of the first and second logic circuitries.

10. The method defined in claim 9 further comprising:

grouping defective logic regions based on the location of the identified defective logic regions.

11. The method defined in claim 8 wherein repairing the defective logic group further comprising:

configuring the spare logic regions of the spare logic group using test equipment to replace the logic regions of the defective logic group.

12. The method defined in claim 11 wherein the spare logic regions are coupled using spare interconnects, wherein replacing the logic further comprising:

selecting the spare interconnects into use to replace the interconnect of the defective logic group.

13. The method defined in claim 8 wherein the logic groups are organized in an order, wherein repairing the defective logic group comprises:

replacing each successive logic group in the order following the defective logic group with a previous logic group.

14. A multi-chip package comprising:

a first integrated circuit having a first logic region and at least one spare logic region;

a second integrated circuit having a second logic region and at least one spare logic region, wherein the first and second integrated circuits include a different number of spare logic regions;

an interconnect coupled between the first logic region of the first integrated circuit and second logic region of the second integrated circuit; and

an additional interconnect that is coupled between the spare logic regions of the first and second integrated circuits, wherein the spare logic regions and the additional interconnect are utilized in response to a defect.

15. The multi-chip package defined in claim 14 wherein the defect can be in any one of the first logic region, second logic region, and interconnect.

16. The multi-chip package defined in claim 14 further comprising:

first multiplexing circuitry that is configured to select the spare logic region of the first integrated circuit when the first logic region is defective.

17. The multi-chip package defined in claim 16 further comprising:

second multiplexing circuitry that is configured to select the spare logic region of the second integrated circuit when the second logic region is defective.

18. The multi-chip package defined in claim 17 wherein the first integrated circuit is mounted on the second integrated circuit, wherein the interconnect and the additional interconnect include through-silicon vias in the first integrated circuit.

19. A multi-chip package comprising:

a first integrated circuit having a first logic region and at least one spare logic region;

a second integrated circuit having a second logic region and at least one spare logic region;

an interconnect coupled between the first logic region of the first integrated circuit and second logic region of the second integrated circuit; and

an additional interconnect that is coupled between the spare logic regions of the first and second integrated circuits, wherein the spare logic regions and the additional interconnect are utilized in response to a defect, wherein the first and second integrated circuits are mounted on an interposer, and wherein the first integrated circuit is placed adjacent to the second integrated circuit.