Apparatus and methods for on-die instrumentation
One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.
1. A receiver for a data link, the receiver comprising:
a data path receiving an input signal from the data link, the data path comprising
a clock data recovery (CDR) loop for obtaining a recovered clock signal from the input signal, and
first sampler circuitry triggered by the recovered clock signal for generating a recovered data signal from the input signal;
a phase interpolator receiving the recovered clock signal and generating a phase-interpolated clock signal; and
decision feedback equalization (DFE) circuitry comprising second sampler circuitry triggered by the recovered clock signal in a first operating mode and by the phase-interpolated clock signal in a second operating mode.
2. The receiver of claim 1 , wherein the first operating mode performs speculative DFE adaptation, and wherein the second operating mode performs on-die instrumentation functionalities.
3. The receiver of claim 1 , wherein a phase of the phase-interpolated clock signal is stepped across a unit interval in the second operating mode.
4. The receiver of claim 3 further comprising:
a bit error rate checker that, in the second operating mode, receives the recovered clock signal, the recovered data signal, and a phase-interpolated data signal which is output by the second sampler circuitry.
5. The receiver of claim 1 further comprising:
a reference voltage generator that provides to the second sampler circuitry a first pair of reference voltages controlled by a DFE adaptation engine in the first operating mode and a second pair of reference voltages controlled by on-die instrumentation logic in the second operating mode.
6. The receiver of claim 5 , wherein a voltage level of the second pair of reference voltages is stepped over a range of voltage levels in the second operating mode.
7. The receiver of claim 1 , wherein the second sampler circuitry comprises a first even sampler and a first odd sampler that utilize a positive-polarity reference voltage and a second even sampler and a second odd sampler that utilize a negative-polarity reference voltage.
8. The receiver of claim 7 , wherein the second sampler circuitry further comprises a series of flip flop circuits after each of the first even sampler, the first odd sampler, the second even sampler, and the second odd sampler.
9. The receiver of claim 8 , wherein the series of flip flop circuits perform resynchronization between a clock domain of the phase-interpolated clock signal and a clock domain of the recovered clock signal.
10. A method of providing both on-die instrumentation and decision feedback equalization in an integrated circuit, the method comprising:
receiving an input signal from a data link;
obtaining a recovered clock signal from the input signal;
generating a recovered data signal from the input signal using a first sampler triggered by the recovered clock signal;
generating a phase-interpolated clock signal by applying phase interpolation to the recovered clock signal;
triggering a second sampler using the recovered clock signal in a first operating mode which performs decision feedback equalization adaptation; and
triggering the second sampler using the phase-interpolated clock signal in a second operating mode so as to generate eye-diagram data for the on-die instrumentation.
11. The method of claim 10 further comprising:
stepping a phase of the phase-interpolated clock signal across a unit interval in the second operating mode.
12. The method of claim 10 further comprising:
determining a bit error rate using the recovered clock signal, the recovered data signal, and a phase-interpolated data signal output from the second sampler in the second operating mode.
13. The method of claim 10 further comprising:
providing to the second sampler a first pair of reference voltages controlled by a DFE adaptation engine in the first operating mode and a second pair of reference voltages controlled by on-die instrumentation logic in the second operating mode.
14. The method of claim 13
stepping a voltage level of the second pair of reference voltages over a range of voltage levels in the second operating mode.
15. The method of claim 10 further comprising:
performing resynchronization between a clock domain of the phase-interpolated clock signal and a clock domain of the recovered clock signal.
16. The method of claim 15 , wherein the second sampler comprises a first even sampler and a first odd sampler that utilize a positive-polarity reference voltage and a second even sampler and a second odd sampler that utilize a negative-polarity reference voltage, and wherein the resynchronization is performed by a series of flip flop circuits after each of the first even sampler, the first odd sampler, the second even sampler, and the second odd sampler.
17. A receiver for a high-speed serial interface, the receiver comprising:
a clock data recovery loop for obtaining a recovered clock signal from a received input signal
a first sampler triggered by the recovered clock signal for generating a recovered data signal from the received input signal;
a phase interpolator generating a phase-interpolated clock signal from the recovered clock signal; and
a second sampler triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode.
18. The receiver of claim 17 , wherein a phase of the phase-interpolated clock signal is stepped across a unit interval in the on-die instrumentation mode.
19. The receiver of claim 17 further comprising:
a bit error rate checker that, in the second operating mode, receives the recovered clock signal, the recovered data signal, and a phase-interpolated data signal which is output by the second sampler circuitry.
20. The receiver of claim 17 further comprising:
a reference voltage generator that provides to the second sampler circuitry a first pair of reference voltages controlled by a decision feedback equalization adaptation engine in the first operating mode and a second pair of reference voltages controlled by on-die instrumentation logic in the second operating mode.