Method and apparatus for relocating design modules while preserving timing closure

1. A method, comprising:

providing a developer environment;

directing, via the developer environment, a compilation of a first circuit design;

directing, via the developer environment, a placement of the first circuit design on a programmable logic device at a first location;

directing, via the developer environment, an optimization of the placed first circuit design to generate a design optimization;

directing, via the developer environment, a preservation of the design optimization of the placed first circuit design after the optimization; and

directing, via the developer environment, an application of the design optimization on a placed design of the first circuit design at a second location.

2. The method of claim 1 , wherein the design optimization comprises a physical design optimization.

3. The method of claim 1 , wherein the design optimization is preserved in a script file interpretable by an electronic design automation tool.

4. The method of claim 1 , wherein the application of the design optimization on the placed design of the first circuit design comprises directing, via the developer environment, a placement change of a portion of the first circuit design.

5. The method of claim 1 , wherein the design optimization comprises a clock path, a timing optimization, a routing optimization, a placement optimization, or any combination thereof.

6. The method of claim 1 , wherein the application of the design optimization on the placed design comprises directing, via the developer environment, a referencing of a displacement option.

7. The method of claim 6 , wherein the displacement option comprises an indication of a relocation of the first circuit design based on an existing placement of the circuit design.

8. The method of claim 6 , wherein the displacement option comprises a specification setting configured to indicate a fanout optimization, logical rewiring optimization, a clock optimization, a placement optimization, or any combination thereof.

9. The method of claim 1 , comprising:

directing, via the developer environment, a routing of the first circuit design on the programmable logic device at the first location using a first portion of routing and a second portion of routing; and

directing, via the developer environment, a routing of the placed design of the first circuit design at the second location using the first portion of routing.

10. The method of claim 1 , comprising directing, via the developer environment, processing circuitry to cause physical configuration of the programmable logic device based at least in part on a result from applying the design optimization on the placed design of the first circuit design at the second location.

11. A system, comprising:

a memory storing a field programmable gate array developer; and

a processing device configurable to execute the field programmable gate array developer, wherein by executing the field programmable gate array developer, the processing device is configured to:

direct, via a developer environment associated with the field programmable gate array developer, a placement of a first circuit design on a programmable logic device based on design optimizations generated in response to a previous compiling of the first circuit design;

direct, via the developer environment, a complication of the first circuit design;

direct, via the developer environment, a preservation of a design optimization of the placed first circuit design after an optimization; and

direct, via the developer environment, an application of the design optimization on a placed design of the first circuit design at a second location.

12. The system of claim 11 , wherein the design optimization comprises a timing preservation.

13. The system of claim 11 , comprising instructions to direct, via the developer environment, a performance of an additional fanout optimization of the placed design based on an initial fanout optimization corresponding to the design optimization.

14. The system of claim 11 , comprising instructions to direct, via the developer environment, a performance of an additional placement optimization based on an initial placement optimization corresponding to the design optimization.

15. The system of claim 11 , comprising instructions to direct, via the developer environment, a configuration of a physical programmable logic device based on a result from an application of the design optimization on the placed design of the first circuit design at the second location.

16. The system of claim 11 , comprising instructions to direct, via the developer environment, a referencing of a displacement option specified by a user.

17. The system of claim 16 , wherein the displacement option comprises a fanout optimization indication, logical rewiring optimization indication, a clock optimization indication, a placement optimization indication, or any combination thereof.

18. A tangible, non-transitory, machine-readable media storing instructions executable by one or more processors of an electronic device, wherein the instructions comprise instructions to:

direct, via a developer environment, a performance of an optimizing action on a first circuit design;

direct, via the developer environment, the performance a placement of the first circuit design on a programmable logic device at a first location;

direct, via the developer environment, the performance of a physical optimization of the placed first circuit design to generate a design optimization;

direct, via the developer environment, a preservation of the design optimization of the placed first circuit design after the design optimization; and

direct, via the developer environment, an application of the design optimization on a placed design of the first circuit design at a second location.

19. The machine-readable media of claim 18 , wherein the optimizing action is configured to direct, via the developer environment, a generation of a netlist corresponding to the first circuit design, and wherein the placement of the first circuit design on the programmable logic device at the first location is based at least in part on the netlist.

20. The machine-readable media of claim 18 , wherein the design optimization comprises a placement preservation, a routing preservation, a timing preservation, or any combination thereof.