Circuits And Methods For Generating Adjustable Signal Pulses That Control Writes To Memory Cells
An integrated circuit includes a memory bit cell having a transistor coupled to a data line and a write pulse generation circuit coupled to the memory bit cell. The write pulse generation circuit generates a pulse in a word line signal that controls the transistor. The write pulse generation circuit adjusts a width of the pulse in the word line signal based on a write time of a write operation to the memory bit cell performed through the data line and the transistor.
1 . An integrated circuit comprising:
a memory bit cell comprising a first transistor coupled to a data line; and
a write pulse generation circuit coupled to the memory bit cell, wherein the write pulse generation circuit generates a first pulse in a word line signal that controls the first transistor, and wherein the write pulse generation circuit adjusts a width of the first pulse in the word line signal based on a write time of a write operation to the memory bit cell performed through the data line and the first transistor.
2 . The integrated circuit of claim 1 , wherein the memory bit cell further comprises a second transistor coupled to an inverse data line, and wherein the write operation to the memory bit cell is performed through the inverse data line and the second transistor.
3 . The integrated circuit of claim 1 , wherein the write pulse generation circuit comprises a second transistor coupled to the data line, a third transistor coupled to cross-coupled inverter circuits in the memory bit cell, and a logic gate circuit comprising a first input coupled to the second transistor and a second input coupled to the third transistor.
4 . The integrated circuit of claim 1 , wherein the write pulse generation circuit comprises an XOR logic gate circuit comprising inputs that are coupled to the data line and to the memory bit cell in response to the first pulse in the word line signal.
5 . The integrated circuit of claim 4 , wherein the write pulse generation circuit further comprises a decoder circuit that generates the first pulse in the word line signal in response to a second pulse in an output signal of the XOR logic gate circuit.
6 . The integrated circuit of claim 1 , wherein the write pulse generation circuit comprises an inverter circuit and an AND gate circuit comprising an input coupled to the inverter circuit, and wherein the inverter circuit and the AND gate circuit generate a second pulse in a rise detect signal in response to a transition in a clock signal.
7 . The integrated circuit of claim 6 , wherein the write pulse generation circuit further comprises a decoder circuit and an XOR gate circuit that generates a third pulse in an output signal in response to the second pulse in the rise detect signal, and wherein the decoder circuit generates the first pulse in the word line signal in response to the third pulse in the output signal.
8 . The integrated circuit of claim 1 , wherein the write pulse generation circuit comprises an AND gate circuit and a decoder circuit that generates the first pulse in the word line signal in response to a second pulse in an output signal of the AND gate circuit, and wherein the AND gate circuit generates the second pulse in the output signal in response to a logic transition in a clock signal.
9 . The integrated circuit of claim 1 , wherein the integrated circuit is a configurable integrated circuit comprising configuration random access memory.
10 . A method for writing a bit to a memory circuit, the method comprising:
generating a first logic transition on a word line that turns on a first access transistor to begin a write of the bit to the memory circuit through a data line and the first access transistor using a pulse generation circuit; and
generating a second logic transition that is opposite the first logic transition on the word line that turns off the first access transistor in response to a completion of the write of the bit to the memory circuit using the pulse generation circuit.
11 . The method of claim 10 , wherein generating the first logic transition on the word line further comprises generating the first logic transition on the word line that turns on a second access transistor to begin the write of an inverted bit to the memory circuit through an inverse data line and the second access transistor.
12 . The method of claim 10 , wherein generating the first logic transition on the word line further comprises generating the first logic transition on the word line in response to a third logic transition in a clock signal.
13 . The method of claim 10 further comprising:
coupling inputs of an XOR logic gate circuit to the data line and the memory circuit through pass gate transistors in response to the first logic transition.
14 . The method of claim 10 further comprising:
decoupling inputs of an XOR logic gate circuit from the data line and the memory circuit through pass gate transistors in response to the second logic transition.
15 . The method of claim 10 , wherein generating the second logic transition on the word line further comprises generating the second logic transition on the word line in response to the data line and a node in the memory circuit having a same logic state.
16 . The method of claim 10 , wherein generating the first logic transition on the word line further comprises generating the first logic transition on the word line using an inverting delay circuit, a first logic gate circuit couped to a first output of the inverting delay circuit, a tri-state inverter circuit coupled to a second output of the first logic gate circuit, and an XOR logic gate circuit coupled to a third output of the tri-state inverter circuit.
17 . A write pulse generation circuit comprising:
a logic gate circuit that causes a first logic transition on a word line to turn on an access transistor that begins a write of a bit to a memory cell through a data line and the first access transistor,
wherein the logic gate circuit causes a second logic transition that is opposite the first logic transition on the word line to turn off the access transistor in response to completion of the write of the bit to the memory cell.
18 . The write pulse generation circuit of claim 17 , wherein the logic gate circuit causes the second logic transition on the word line in response to the data line and a node in the memory cell having a same logic state.
19 . The write pulse generation circuit of claim 17 further comprising:
pass gate transistors that couple inputs of the logic gate circuit to the data line and the memory cell in response to the first logic transition and that decouple the inputs of the logic gate circuit from the data line and the memory cell in response to the second logic transition.
20 . The write pulse generation circuit of claim 17 , wherein the logic gate circuit is an XOR logic gate circuit.