Configuring a programmable logic device using a configuration bit stream without phantom bits
View Patent ↗Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits.
1. A circuit including configuration elements comprising:
a bit stream generation circuit to receive a first configuration bit stream including a first header portion and a first configuration bit portion, and to generate a second configuration bit stream used to configure the configuration elements of the circuit, the second configuration bit stream including at least one padding bit and at least one bit from the first configuration bit portion based on the first header portion, the first header portion including data used by the bit stream generation circuit to determine a distribution of the configuration elements in the circuit, and the bit stream generation circuit including the at least one padding bit in the second configuration bit stream based on the distribution of configuration elements.
2. The circuit of claim 1 , wherein the at least one padding bit corresponds to a location in the circuit without a corresponding configuration element.
3. The circuit of claim 1 , wherein the first header portion indicates information of the circuit, the information of the design of the circuit indicating a distribution of resource types of the circuit.
4. The circuit of claim 3 , wherein the information of the design of the circuit is stored in a memory of the circuit.
5. The circuit of claim 1 , wherein the first header portion is positioned adjacent to the first configuration bit portion in the first configuration bit stream.
6. The circuit of claim 1 , wherein the first configuration bit stream includes a first portion and a second portion, the first portion including the first header portion and the first configuration bit portion, the second portion including a second header portion and a second configuration bit portion.
7. The circuit of claim 6 , wherein the first header portion is positioned adjacent to the first configuration bit portion, the first configuration bit portion is positioned adjacent to the second header portion, and the second header portion is positioned adjacent to the second configuration bit portion.
8. The circuit of claim 1 , wherein the at least one bit from the first configuration bit portion included in the second configuration bit stream corresponds to a location in the circuit with a corresponding configuration element.
9. The circuit of claim 1 , further comprising:
registers to store bits from the second configuration bit stream, the bits stored in the registers used to configure the configuration elements.
10. The circuit of claim 1 , wherein the distribution of configuration elements indicates a bit in the second bit stream corresponds to a location in the circuit without a corresponding configuration element.
11. A device comprising:
a bit stream generation circuit for receiving a first configuration bit stream including a first header portion and a first configuration bit portion;
storage circuit for storing information associated with the first header portion, wherein the bit stream generation circuit is further for generating a second configuration bit stream used to configure the configuration elements of the circuit, the second configuration bit stream including at least one padding bit and at least one bit from the first configuration bit portion based on information in the storage circuit, the information in the storage circuit used by the bit stream generation circuit to determine a distribution of configuration elements in the device, and the bit stream generation circuit including the at least one padding bit in the second configuration bit stream based on the distribution of configuration elements.
12. The device of claim 11 , wherein the configuration elements are to be configured based on the second configuration bit stream.
13. The device of claim 12 , wherein the information in the storage circuit indicates a distribution of the configuration elements or locations in a configurable circuit without a corresponding configuration element.
14. The device of claim 11 , wherein the at least one padding bit corresponds to a location in a configurable circuit without a corresponding configuration element.
15. The device of claim 11 , wherein the first header portion indicates information of a design of a configurable circuit, the information of the design of the configurable circuit indicating a distribution of resource types of the configurable circuit.
16. The device of claim 11 , wherein the first configuration bit stream includes a first portion and a second portion, the first portion including the first header portion and the first configuration bit portion, the second portion including a second header portion and a second configuration bit portion.
17. The device of claim 16 , wherein the first header portion is positioned adjacent to the first configuration bit portion, the first configuration bit portion is positioned adjacent to the second header portion, and the second header portion is positioned adjacent to the second configuration bit portion.
18. A method for configuring a semiconductor device having configuration elements, the method comprising:
receiving, by the semiconductor device, a first configuration bit stream including a first header portion and a first configuration bit portion;
determining a distribution of the configuration elements based on the first header portion;
generating, by the semiconductor device, a second configuration bit stream including at least one padding bit and at least one bit from the first configuration bit portion, wherein the at least one padding bit is included in the second configuration bit stream based on the distribution of configuration elements indicating a bit in the second bit stream corresponds to a location in the semiconductor device without a corresponding configuration element; and
configuring the configuration elements in the semiconductor device based on the second bit stream.
19. The method of claim 18 , further comprising:
storing, by the semiconductor device, information associated with the first header portion in a memory.
20. The method of claim 18 , wherein the at least one padding bit corresponds to a location in the semiconductor device without a corresponding configuration element.
21. The method of claim 18 , wherein the first header portion indicates information of a design of a configurable circuit, the information of the design of the configurable circuit indicating a distribution of resource types of the configurable circuit.
22. The method of claim 18 , wherein the first header portion is positioned adjacent to the first configuration bit portion in the first configuration bit stream.
23. The method of claim 18 , wherein the first configuration bit stream includes a first portion and a second portion, the first portion including the first header portion and the first configuration bit portion, the second portion including a second header portion and a second configuration bit portion, wherein the first header portion is positioned adjacent to the first configuration bit portion, the first configuration bit portion is positioned adjacent to the second header portion, and the second header portion is positioned adjacent to the second configuration bit portion.