IP Library Granted Patent US 7,415,693
Granted Patent B1
US 7,415,693 · App. 10/851,355 · Granted Aug 19, 2008

Method and apparatus for reducing synthesis runtime

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Quick Facts
Patent No.
US 7,415,693
App. No.
10/851,355
Granted
Aug 19, 2008
Kind
B1
Abstract

A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.

Claims (42)

1. A method for designing a system, comprising:

caching a representation of a first subnet with a synthesis result of the first subnet that describes a functionally equivalent subnet; and

utilizing the synthesis result of the first subnet for a second subnet locatable anywhere in the system in response to determining that a representation of the second subnet is identical to the representation of the first subnet.

2. The method of claim 1 , wherein the synthesis result comprises a sum-of-products representation of the first subnet.

3. The method of claim 1 , wherein the first subnet comprises a cone of simple logic gates with only one output and one or more inputs.

4. The method of claim 1 , further comprising identifying a subnet in a synthesis netlist.

5. The method of claim 4 , wherein identifying a subnet comprises identifying a cone of logic with one output and one or more inputs.

6. The method of claim 4 , wherein identifying a subnet comprises identifying a connected component of combinational logic.

7. The method of claim 4 , wherein identifying a subnet comprises identifying a connected component of arbitrary elements in the synthesis netlist.

8. The method of claim 1 , further comprising:

performing a synthesis procedure on the first subnet to generate the synthesis result;

determining whether the synthesis result is useful to the system.

9. A method for designing a system, comprising:

determining whether a subnet with identified characteristics has been previously processed;

performing a synthesis procedure on a first subnet with the identified characteristic in response to determining that the subnet with the identified characteristics has not been previously processed; and

storing synthesis results associated with the synthesis procedure that describes a functionally equivalent subnet with a representation of the first subnet so that it is used for a second subnet located anywhere in the system.

10. The method of claim 9 , wherein determining whether the subnet with the identified characteristics has been previously processed comprises searching a cache for a representation of the subnet.

11. The method of claim 9 , wherein performing the synthesis procedure comprises collapsing the first subnet into a sum-of-products.

12. The method of claim 11 , further comprising factoring the sum-of-products.

13. The method of claim 9 , wherein performing the synthesis procedure comprises identifying a subcone that has a small number of inputs and a large number of internal nodes.

14. The method of claim 13 , further comprising re-factoring the subcone into a smaller cone.

15. The method of claim 9 , further comprising utilizing the synthesis result associated with the synthesis procedure on a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.

16. The method of claim 9 , wherein performing the synthesis procedure comprises unmapping a look-up table into a cone of simple gates.

17. A machine-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which, when executed by a processor, causes the processor to perform:

caching a representation of a first subnet with a synthesis result of the first subnet, wherein the first subnet describes a cone of simple logic gates with only one output and one or more inputs; and

utilizing the synthesis result of the first subnet for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.

18. The machine-readable medium of claim 17 , further comprising identifying a subnet in a synthesis netlist.

19. The machine-readable medium of claim 18 , wherein identifying a subnet comprises identifying a cone of logic.

20. The machine-readable medium of claim 18 , wherein identifying the subnet comprises identifying a connected component of combinational logic.

21. The machine-readable medium of claim 18 , wherein identifying a subnet comprises identifying a connected component of arbitrary elements in a synthesis netlist.

22. A system designer, comprising:

a procedure execution unit that executes a synthesis procedure on a first subnet in a system to generate a synthesis result that describes a functionally equivalent subnet; and

a cache unit that stores the synthesis result generated by the procedure execution unit with a representation of the first subnet so that the synthesis result is used by a second subnet located anywhere in the system.

23. The system designer of claim 22 , further comprising a synthesis manager that utilizes the synthesis result for the first subnet on a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.

24. The system designer of claim 22 , wherein the procedure execution unit generates a sum-of-products representation of the first subnet.

25. The system designer of claim 22 , wherein the procedure execution unit generates an indication of whether the first subnet has a subcone with a small number of inputs and large number of internal nodes, and whether re-factoring the subcone would improve the system.

26. The system designer of claim 22 , wherein the procedure execution unit generates a subnet having simple gates with the same function as the first subnet.

27. The system designer of claim 22 , further comprising a subnet identification unit that identifies subnets in the synthesis netlist.

28. The system designer of claim 22 , wherein the synthesis procedure unmaps a look-up table into a cone of simple gates.

29. A method for designing a system, comprising:

caching a representation of a first subnet with a synthesis result of the first subnet, wherein the first subnet describes a cone of simple logic gates with only one output and one or more inputs; and

utilizing the synthesis result of the first subnet for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2004
From: ANTWERPEN, BABETTE VAN; BAECKLER, GREGG WILLIAM; YUAN, JINYONG
To: ALTERA CORPORATION
Reel/Frame 015383/0877 →