Compensation network using an on-die compensation inductor

1. An integrated circuit (IC) with an on-die compensation network, comprising:

a compensation inductor of the IC, such that one terminal of the compensation inductor is coupled to a bump pad; and

a metal layer underneath the compensation inductor, such that another terminal of the compensation inductor is coupled to the metal layer of the IC, wherein the metal layer routes input and output signals from the integrated circuit, and wherein the compensation inductor is coupled in a pi-configuration on the IC to compensate for capacitances of the bump pad and the metal layer.

2. The integrated circuit of claim 1 , wherein the pi configuration further comprises:

the compensation inductor coupled to a capacitance of the bump pad and a capacitance of the metal layer underneath the compensation inductor.

3. The integrated circuit of claim 1 , wherein a value of the compensation inductor is determined by a capacitance of the bump pad and the metal layer, and a capacitance and an inductance of a package and a printed circuit board coupled to the bump pad.

4. The integrated circuit of claim 1 , wherein the compensation inductor is located underneath the bump pad.

5. The integrated circuit of claim 1 , wherein the compensation inductor is implemented as a spiral inductor.

6. The integrated circuit of claim 1 , wherein the compensation inductor is implemented using an existing metal layer closest to a metal layer of the bump pad.

7. The integrated circuit of claim 5 , wherein the compensation inductor is implemented using a plurality of metal layers.

8. The integrated circuit of claim 1 , wherein the pi-configuration minimizes return loss and insertion loss due to on-die, package, and printed circuit board parasitics.

9. The integrated circuit of claim 1 , wherein the bump pad is coupled to one of a wirebond or a solder bump.

10. An electronic module with an on-die compensation network, comprising:

a printed circuit board;

a package coupled to the printed circuit board; and

an integrated circuit coupled to the package, such that the package transmits input and receives output from the printed circuit board to the integrated circuit, the integrated circuit having an on-die matching network compensating for an inductance and a capacitance of the printed circuit board and the package.

11. The electronic module of claim 10 , wherein the on-die matching network further comprises:

a compensation inductor coupled in a pi-configuration to a bump pad and a metal layer underneath the compensation inductor.

12. The electronic module of claim 10 , wherein the on-die matching network minimizes loss based on parasitics of the integrated circuit, the package, and the printed circuit board.

13. The electronic module of claim 11 , wherein a value of the compensation inductor of the on-die matching network is determined by a capacitance of the bump pad and the metal layer, and a capacitance and an inductance of the package and the printed circuit board.

14. The electronic module of claim 11 , wherein a diameter of the compensation inductor is less than a diameter of the bump pad.

15. The electronic module of claim 11 , wherein the metal layer routes input and output from the integrated circuit to the bump pad.

16. A method of designing an integrated circuit with an on-die compensation network, comprising:

determining a capacitive and an inductive impedance value associated with a printed circuit board and a capacitive and an inductive impedance value associated with a package;

determining a capacitive impedance value associated with a bump pad of the integrated circuit, and an on-die capacitive impedance value associated with the integrated circuit;

calculating a size of a compensation inductor according to the impedance values of the printed circuit board, the package, the bump pad of the integrated circuit, and the integrated circuit;

coupling the compensation inductor to the bump pad and a metal layer of the integrated circuit in a pi-configuration, wherein the metal layer routes input and output from the integrated circuit; and

storing a design of the integrated circuit for manufacturing.

17. The method of claim 16 , wherein coupling the compensation inductor further comprises:

calculating a number of turns of the compensation inductor based on the impedance values of the printed circuit board and the package.

18. The method of claim 16 , wherein coupling the compensation inductor further comprises:

implementing the compensation inductor on a plurality of metal layers of the integrated circuit closest to the bump pad.

19. The method of claim 16 , wherein coupling the compensation inductor further comprises:

placing the compensation inductor underneath the bump pad.

20. The method of claim 16 , further comprising:

fabricating the compensation inductor with a diameter less than a diameter of a solder pad.