Routing-efficient time division multiplexing (TDM) data path circuitry

1. Time division multiplexing (TDM) circuitry, comprising:

a first rotary multiplexer circuit configured to receive N-bit wide data in accordance to a time division multiple access (TDMA), wherein the N-bit wide data comprises multiple sets of M-bit wide data, and wherein the first rotary multiplexer circuit is configured to:

receive a first set of M-bit wide data, a second set of M-bit wide data, and a third set of M-bit wide data of the multiple sets of M-bit wide data;

rotate the second set of M-bit wide data by a first shifting factor to generate a corresponding second rotated set of M-bit wide data;

rotate the third set of M-bit wide data by a second shifting factor to generate a corresponding third rotated set of M-bit wide data; and

a memory circuit coupled to the first rotary multiplexer circuit, wherein the memory circuit is configured to store the first set of M-bit wide data, the second rotated set of M-bit wide data, and the third rotated set of M-bit wide data.

2. The TDM circuitry of claim 1 , comprising:

a second rotary multiplexer circuit configured to read a set of bits from the memory circuit and output the set of the bits serially, wherein one or more bits within the set of the bits is k-th bits of each of the M-bit wide data, wherein k is an integer value greater than 0.

3. The TDM circuitry of claim 2 , comprising:

a plurality of channels coupled to the second rotary multiplexer circuit, wherein each one of the plurality of the channels transmits one of the k-th bit outputted from the second rotary multiplexer circuit.

4. The TDM circuitry of claim 3 , wherein the value of the N is 320 and the value of the M is 32.

5. The TDM circuitry of claim 3 , wherein the memory circuit comprises:

a plurality of memory banks, wherein each memory bank comprises a plurality of memory elements addressable based on an identical range of addresses; and

an address controller to generate an address for addressing the plurality of the memory elements.

6. The TDM circuitry of claim 1 , wherein each bit from the second rotated set of M-bit wide data is stored in the memory elements having identical addresses in a plurality of the memory banks.

7. The TDM circuitry of claim 2 , wherein the second rotary multiplexer circuit is configured to rotate the sets of bits read from the memory circuit when the value of k is more than 1.

8. The TDM circuitry of claim 2 , wherein the first and second rotary multiplexer circuits comprise barrel shifter circuits.

9. An integrated circuit device, comprising:

a plurality of transceiver circuits configured to receive data from an external integrated circuit device and generate N-bit wide data; and

time division multiplexing (TDM) circuitry configured to receive the N-bit wide data in accordance to time division multiple access (TDMA) and serially output an M-bit wide data, wherein the TDM circuitry comprises 4*N routings and a first rotary multiplexer circuit, wherein the first rotary multiplexer circuit is configured to:

receive a first set of the M-bit wide data, a second set of the M-bit wide data, and a third set of the M-bit wide data;

rotate the second set of the M-bit wide data by a first shifting factor to generate a corresponding second rotated set of the M-bit wide data;

rotate the third set of the M-bit wide data by a second shifting factor to generate a corresponding third rotated set of the M-bit wide data; and

a memory circuit coupled to the first rotary multiplexer circuit, wherein the memory circuit is configured to store the first set of the M-bit wide data, the second rotated set of the M-bit wide data, and the third rotated set of the M-bit wide data.

10. The integrated circuit of claim 9 , comprising:

a processor circuit configured to couple to the TDM circuitry and process the M-bit wide data received from the TDM circuitry.

11. The integrated circuit device of claim 10 , wherein the processor circuit comprises a processor architecture comprising Advanced RISC Machines (ARM) architecture or Nois architecture, or a combination thereof.

12. The integrated circuit device of claim 9 , wherein each of the plurality of the transceiver circuits is configured to transfer data at approximately 10 gigabits/second (Gbps).

13. The integrated circuit device of claim 9 , wherein the TDM circuitry comprises:

a second rotary multiplexer circuit configured to read a set of bits from the memory circuit and output the set of the bits serially, wherein the set of the bits includes k-th bits of each of the M-bit wide data, wherein k is an integer value greater than 0.

14. The integrated circuit device of claim 9 , wherein value of the N is 320 and the TDM circuitry includes 1280 routings.

15. A method of operating time division multiplexing (TDM) circuitry, the method comprising:

receiving N-bit wide data in parallel from one or more transceiver circuits, wherein the N-bit wide data is separated into multiple sets of M-bit wide data;

using a first rotary multiplexer circuit to:

receive a first set of the M-bit wide data, a second set of the M-bit wide data, and a third set of the M-bit wide data of the multiple sets of the M-bit wide data;

rotate the second set of the M-bit wide data by a first shifting factor to generate a corresponding second rotated set of the M-bit wide data;

rotate the third set of the M-bit wide data by a second shifting factor to generate a corresponding third rotated set of the M-bit wide data; and

storing the first set of the M-bit wide data, the second rotated set of the M-bit wide data, and the third rotated set of the M-bit wide data.

16. The method of claim 15 , comprising:

using a second rotary multiplexer circuit to read a set of k-th bits from each of the first set, the second rotated set, and the third rotated set of M-bit wide data, wherein the k is an integer and has a value more than 0; and

using the second rotary multiplexer circuit, outputting the set of k-th bits.

17. The method of claim 16 , comprising:

when the value of k is more than 1, rotating the set of k-th bits; and

after rotating the set of k-th bits, outputting the set of k-th bits.

18. The method of claim 15 , wherein a value of N is 320 and a value of M is 10.

19. The method of claim 15 , wherein the first rotary multiplexer circuit comprises barrel shifter circuitry.

20. The method of claim 16 , wherein the second rotary multiplexer circuit comprises barrel shifter circuitry.