Power gated lookup table circuitry
A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.
1. An integrated circuit, comprising:
lookup table circuitry that comprises:
a tristate inverting circuit that includes only three transistors coupled in series; and
a memory element that controls at least two of the three transistors in the tristate inverting circuit.
2. The integrated circuit of claim 1 , wherein the three transistors comprise two p-channel transistors and one n-channel transistor.
3. The integrated circuit of claim 1 , wherein the three transistors comprise two n-channel transistors and one p-channel transistor.
4. The integrated circuit of claim 1 , wherein the memory element comprises a configuration random-access memory cell.
5. The integrated circuit of claim 1 , wherein the tristate inverting circuit has an output that is coupled between the at least two transistors controlled by the memory element.
6. The integrated circuit of claim 1 , further comprising:
a first power supply line; and
a second power supply line, wherein the three transistors of the tristate inverting circuit are coupled in series between the first and second power supply lines.
7. The integrated circuit of claim 1 , wherein the tristate inverting circuit is part of a multiplexing circuit.
8. The integrated circuit of claim 7 , wherein the multiplexing circuit comprises an additional tristate inverting circuit.
9. The integrated circuit of claim 8 , wherein the tristate inverting circuit and the additional tristate inverting circuit share the same output.
10. The integrated circuit of claim 1 , wherein the tristate inverting circuit further comprises an inverter coupled between gate terminals of the at least two transistors controlled by the memory element.
11. An integrated circuit, comprising:
lookup table circuitry that includes a tristate inverting circuit, wherein the tristate inverting circuit comprises:
a first transistor of a given channel type; and
a second transistor of the given channel type, wherein the second transistor is coupled in series with the first transistor, and wherein the first and second transistors receive the same control signal.
12. The integrated circuit of claim 11 , wherein the first and second transistors of the given channel type are n-channel transistors having gate terminals shorted to each other.
13. The integrated circuit of claim 11 , wherein the first and second transistors of the given channel type are p-channel transistors having gate terminals shorted to each other.
14. The integrated circuit of claim 11 , wherein the tristate inverting circuit further comprises:
an output; and
a power supply terminal, wherein the first and second transistors are coupled in series between the output and the power supply terminal.
15. The integrated circuit of claim 11 , wherein the tristate inverting circuit further comprises:
a third transistor coupled in series with the first and second transistors;
a fourth transistor coupled in series with the first, second, and third transistors, wherein the third and fourth transistors receive a static control signal from a memory cell.
16. An integrated circuit, comprising:
lookup table circuitry that comprises:
a tristate inverting circuit having an output; and
a pass transistor coupled to the output of the tristate inverting circuit, wherein the pass transistor and at least one transistor in the tristate inverting circuit receive the same control signal.
17. The integrated circuit of claim 16 , wherein the lookup table circuitry further comprises an additional pass transistor coupled in parallel with the pass transistor.
18. The integrated circuit of claim 16 , wherein the tristate inverting circuit further includes first and second transistors that receive a static control bit from a memory cell, and wherein the at least one transistor is coupled in series with the first and second transistors.
19. The integrated circuit of claim 16 , wherein the tristate inverting circuit includes only three transistors.
20. The integrated circuit of claim 16 , wherein the lookup table circuitry further comprises:
an additional tristate inverting circuit having an output; and
an additional pass transistor coupled to the output of the additional tristate inverting circuit, wherein the pass transistor is directly connected to the additional pass transistor.